Description: Use language to read and write verilog CY7C68013A based USB device, use, easy to get started.
To Search:
File list (Check if you may need any files):
USB_CY7C68013_Verilog\readme.txt
.....................\usb_wr_firmware\build.bat
.....................\...............\bulkloop
.....................\...............\bulkloop.c
.....................\...............\bulkloop.iic
.....................\...............\bulkloop.iic.bak
.....................\...............\bulkloop.lnp
.....................\...............\bulkloop.LST
.....................\...............\bulkloop.M51
.....................\...............\bulkloop.OBJ
.....................\...............\bulkloop.Opt
.....................\...............\bulkloop.plg
.....................\...............\bulkloop.__i
.....................\...............\bulkloop_Opt.Bak
.....................\...............\bulkloop_Uv2.Bak
.....................\...............\dscr.a51
.....................\...............\dscr.LST
.....................\...............\dscr.OBJ
.....................\...............\dscr._ia
.....................\...............\Ezusb.lib
.....................\...............\EZWin2K.INF
.....................\...............\firmware.c
.....................\...............\fw.c
.....................\...............\fw.LST
.....................\...............\fw.OBJ
.....................\...............\fw.__i
.....................\...............\Fx2.h
.....................\...............\fx2regs.h
.....................\...............\fx2regs.inc
.....................\...............\fx2sdly.h
.....................\...............\hex2c.exe
.....................\...............\readme.txt
.....................\...............\syncdly.h
.....................\...............\USBJmpTb.OBJ
.....................\...............\usb_wr_in
.....................\...............\usb_wr_in.hex
.....................\...............\usb_wr_in.lnp
.....................\...............\usb_wr_in.M51
.....................\...............\usb_wr_in.Opt
.....................\...............\usb_wr_in.plg
.....................\...............\usb_wr_in.Uv2
.....................\...............\usb_wr_in_Opt.Bak
.....................\...............\usb_wr_in_Uv2.Bak
.....................\.......Verilog\read me.txt
.....................\..............\transcript
.....................\..............\USB_wr.asm.rpt
.....................\..............\USB_wr.cdf
.....................\..............\USB_wr.done
.....................\..............\USB_wr.dpf
.....................\..............\USB_wr.fit.smsg
.....................\..............\USB_wr.fit.summary
.....................\..............\USB_wr.flow.rpt
.....................\..............\USB_wr.jdi
.....................\..............\USB_wr.map.rpt
.....................\..............\USB_wr.map.summary
.....................\..............\USB_wr.merge.rpt
.....................\..............\USB_wr.pin
.....................\..............\USB_wr.qpf
.....................\..............\USB_wr.qsf
.....................\..............\USB_wr.qws
.....................\..............\USB_wr.tan.summary
.....................\..............\USB_wr.v
.....................\..............\USB_wr.v.bak
.....................\usb_wr_firmware
.....................\usb_wr_Verilog
USB_CY7C68013_Verilog
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