Description: Interconnect delay simulation. In order to effectively solve the problems of field programmable gate array power delay product development issues, the use of integrated circuit interconnect structure and the sub-circuit low-voltage swing
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interconnect\1.1.ic0
............\1.1.lis
............\1.1.mt0
............\1.1.pa0
............\1.1.sp
............\1.1.sp.bak
............\1.1.st0
............\1.1.tr0
............\1.2.ic0
............\1.2.lis
............\1.2.pa0
............\1.2.sp
............\1.2.st0
............\1.2.tr0
............\1.3.1.ic0
............\1.3.1.lis
............\1.3.1.mt0
............\1.3.1.pa0
............\1.3.1.sp
............\1.3.1.sp.bak
............\1.3.1.st0
............\1.3.1.tr0
............\1.3.2.ic0
............\1.3.2.lis
............\1.3.2.mt0
............\1.3.2.pa0
............\1.3.2.sp
............\1.3.2.st0
............\1.3.2.tr0
............\lilei1.ic0
............\lilei1.lis
............\lilei1.pa0
............\lilei1.sp
............\lilei1.st0
............\lilei1.tr0
............\MIL.log
interconnect
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