- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2013-03-28
- Downloads:
- 0 Times
- Uploaded by:
- win
Description: -- This decoder in VHDL samples the signals using all four available edges of
-- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on
-- falling(A), and sample(A) on rising(B).
To Search:
File list (Check if you may need any files):
QDEC.vhd
Download