Description: Clock, timer, 23 hours, 59 minutes, 59 seconds of clock, automatic binary timing, Verilog prepared
To Search:
File list (Check if you may need any files):
clock_timer
...........\clock_timer.asm.rpt
...........\clock_timer.bsf
...........\clock_timer.done
...........\clock_timer.dpf
...........\clock_timer.fit.rpt
...........\clock_timer.fit.smsg
...........\clock_timer.fit.summary
...........\clock_timer.flow.rpt
...........\clock_timer.map.rpt
...........\clock_timer.map.summary
...........\clock_timer.pin
...........\clock_timer.pof
...........\clock_timer.qpf
...........\clock_timer.qsf
...........\clock_timer.qws
...........\clock_timer.sof
...........\clock_timer.tan.rpt
...........\clock_timer.tan.summary
...........\clock_timer.v
...........\clock_timer.v.bak
...........\clock_timer_assignment_defaults.qdf
...........\db
...........\..\clock_timer.db_info
...........\..\clock_timer.eco.cdb
...........\..\clock_timer.map.qmsg
...........\..\clock_timer.sld_design_entry.sci
...........\fpga_starter_pin.tcl
Download