- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2013-04-13
- Downloads:
- 0 Times
- Uploaded by:
- 李雪
Description: The various modules connected to the total program, frequency meter design that are connected to the divider, controllers, counters, gate control, latches, display, test frequency range of: 10Hz ~~ 100MHz speed: gate time 1S when maximum readings 999.999KHz second gear: the gate time 0.1S maximum reading 9999.99KHz third tranche: gate time 0.01S, the maximum readings for 99999.9KHz. Readings with six BCD seven segment LED display.
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final.vhd
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