Description: application note focuses on the design of a synchronous FIFO master interface. A master initiates transfers, drives an address bus (if present), and usually supplies a clock to the slave. The slave device used in this design is another FX3 device whose GPIF II unit is programmed to act as a Slave FIFO. To test the design, we connected two FX3 Development Kits (DVKs) using each one' s GPIF II interface, and one FX3 DVK is programmed to act as the FIFO slave unit. The behavior for this Slave FIFO interface is detailed in this note before delving into the FIFO master implementation. For more details about a Slave FIFO interface, see AN65974, Designing with the EZ-USB FX3 ™ Slave FIFO Interface.
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File list (Check if you may need any files):
Source files of FX3 firmware and GPIF II projects
.................................................\bin
.................................................\...\8192_Count.hex
.................................................\...\AutoMaster.img
.................................................\...\AutoSlave.img
.................................................\FX3 Firmware
.................................................\............\.metadata
.................................................\............\.........\.log
.................................................\............\.........\.mylyn
.................................................\............\.........\......\contexts
.................................................\............\.........\......\repositories.xml.zip
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.................................................\............\.........\........\org.eclipse.cdt.core
.................................................\............\.........\........\org.eclipse.cdt.make.core
.................................................\............\.........\........\.........................\AutoMaster.sc
.................................................\............\.........\........\.........................\AutoSlave.sc
.................................................\............\.........\........\.........................\SlaveFifoSync.sc
.................................................\............\.........\........\.........................\specs.c
.................................................\............\.........\........\.........................\specs.cpp
.................................................\............\.........\........\org.eclipse.cdt.managedbuilder.core
.................................................\............\.........\........\org.eclipse.cdt.ui
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