采用Verilog HDL RTL 描述完成数字钟_v1.docx
digital_clock
.............\design_source
.............\.............\bcd_counter.v
.............\.............\binbcd8.v
.............\.............\clk_1s.v
.............\.............\count_top.v
.............\.............\counter.v
.............\.............\display.v
.............\.............\seg7.v
.............\xdc
.............\...\clock.xdc