Description: The CAN receiver has a total of 5 stages to receive the FIFO, and in the reception process, the received messages will be in 5
Save in level input FIFO. In CAN, 5 message buffers are passed through conversion during work
Alternately mapped to each memory area of the microcontroller. RxBG (background receive buffer) only with MSCAN
Associated, the foreground receive buffer can be addressed via the CPU.
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