misp 5 stage pipeline

pipelined-mips-cpu-master
.........................\src
.........................\...\ALU.v
.........................\...\ALU_Control.v
.........................\...\Adder.v
.........................\...\Control.v
.........................\...\Data_Memory.v
.........................\...\EX_MEM.v
.........................\...\Equal.v
.........................\...\Forwarding.v
.........................\...\Hazard_Detection.v
.........................\...\ID_EX.v
.........................\...\IF_ID.v
.........................\...\Instr_Memory.v
.........................\...\MEM_WB.v
.........................\...\MUX_10bit.v
.........................\...\MUX_2x32bit.v
.........................\...\MUX_3x32bit.v
.........................\...\MUX_5bit.v
.........................\...\PC.v
.........................\...\Pipelined_CPU.v
.........................\...\Register_File.v
.........................\...\Sign_Extend.v
.........................\...\Testbench.v

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