with a DPLL CPLD, VHDL or V language.

DPLL0227+V+qt6
..............\db
..............\..\dpll.asm.qmsg
..............\..\dpll.cbx.xml
..............\..\dpll.cmp.cdb
..............\..\dpll.cmp.hdb
..............\..\dpll.cmp.kpt
..............\..\dpll.cmp.logdb
..............\..\dpll.cmp.rdb
..............\..\dpll.cmp.tdb
..............\..\dpll.cmp0.ddb
..............\..\dpll.dbp
..............\..\dpll.db_info
..............\..\dpll.eco.cdb
..............\..\dpll.eds_overflow
..............\..\dpll.fit.qmsg
..............\..\dpll.hier_info
..............\..\dpll.hif
..............\..\dpll.map.cdb
..............\..\dpll.map.hdb
..............\..\dpll.map.logdb
..............\..\dpll.map.qmsg
..............\..\dpll.pre_map.cdb
..............\..\dpll.pre_map.hdb
..............\..\dpll.psp
..............\..\dpll.rtlv.hdb
..............\..\dpll.rtlv_sg.cdb
..............\..\dpll.rtlv_sg_swap.cdb
..............\..\dpll.sgdiff.cdb
..............\..\dpll.sgdiff.hdb
..............\..\dpll.signalprobe.cdb
..............\..\dpll.sim.hdb
..............\..\dpll.sim.qmsg
..............\..\dpll.sim.rdb
..............\..\dpll.sim.vwf
..............\..\dpll.sld_design_entry.sci
..............\..\dpll.sld_design_entry_dsc.sci
..............\..\dpll.syn_hier_info
..............\..\dpll.tan.qmsg
..............\..\wed.zsf
..............\dpll.acf
..............\dpll.asm.rpt
..............\dpll.done
..............\dpll.fit.rpt
..............\dpll.fit.smsg
..............\dpll.fit.summary
..............\dpll.flow.rpt
..............\dpll.hif
..............\dpll.map.rpt
..............\dpll.map.summary
..............\dpll.mmf
..............\dpll.pin
..............\dpll.pof
..............\dpll.qpf
..............\dpll.qsf
..............\dpll.qws
..............\dpll.sim.rpt
..............\dpll.sof
..............\dpll.tan.rpt
..............\dpll.tan.summary
..............\dpll.v
..............\dpll.vwf
..............\全数字锁相环的verilog源代码.doc

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