Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: times Download
 Description: Counter, using VHDL realization frequency first 6 hours, 10 minutes and then the frequency, frequency of 24 minutes, at the same time to do calendar
 Downloaders recently: [More information of uploader kl19880211]
 To Search:
File list (Check if you may need any files):
新建 Microsoft Word 文档.doc
    

CodeBus www.codebus.net