Booth_mul4_v
............\controller.v
............\controller.v.bak
............\datapath.v
............\datapath.v.bak
............\db
............\..\mul4.atom.rvd
............\..\mul4.cbx.xml
............\..\mul4.cmp.rdb
............\..\mul4.dbp
............\..\mul4.db_info
............\..\mul4.eco.cdb
............\..\mul4.hier_info
............\..\mul4.hif
............\..\mul4.map.cdb
............\..\mul4.map.hdb
............\..\mul4.map.logdb
............\..\mul4.map.qmsg
............\..\mul4.pre_map.cdb
............\..\mul4.pre_map.hdb
............\..\mul4.psp
............\..\mul4.rpp.qmsg
............\..\mul4.rtlv.hdb
............\..\mul4.rtlv_sg.cdb
............\..\mul4.rtlv_sg_swap.cdb
............\..\mul4.sgate.rvd
............\..\mul4.sgate_sm.rvd
............\..\mul4.sgdiff.cdb
............\..\mul4.sgdiff.hdb
............\..\mul4.sld_design_entry.sci
............\..\mul4.sld_design_entry_dsc.sci
............\..\mul4.smp_dump.txt
............\..\mul4.syn_hier_info
............\mul4.cr.mti
............\mul4.done
............\mul4.flow.rpt
............\mul4.map.rpt
............\mul4.map.summary
............\mul4.mpf
............\mul4.qpf
............\mul4.qsf
............\mul4.qws
............\mul4.v
............\mul4.v.bak
............\mul4_description.txt
............\t_mul4.v
............\t_mul4.v.bak
............\vsim.wlf
............\work
............\....\controller
............\....\..........\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\datapath
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\mul
............\....\...\verilog.asm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\t_mul4
............\....\......\verilog.asm
............\....\......\_primary.dat
............\....\......\_primary.vhd
............\....\_info