yuandaima FPGA multi-function digital clock, descr - CodeBus

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VHDL-FPGA-Verilog

Title: yuandaima

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
lijingchao5555

Description: FPGA multi-function digital clock, description language VHDL, Quartus Ⅱ software environment

Downloaders recently: [More information of uploader lijingchao5555]

To Search:

[VerilogDHLdigitalclock.Rar] - Verilog language used in the preparation
[ssz] - Digital clock, which is written by VHDL,
[Widget_Watch_VHDL] - Features:(1) digital clock (2) digital s

File list (Check if you may need any files):

yuandaima.vhd

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