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VHDL-FPGA-Verilog
Title:
exer1
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Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
54kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
ltltll
Description:
verilog big job title, description of a remote control with Verilog simulation and synthesis of the circuit
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File list
(Check if you may need any files):
exer1\exer1_report.doc .....\modulator.v .....\test_bench.v exer1 .....\要求.doc
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