Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: sfifo Download
 Description: verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
 Downloaders recently: [More information of uploader water4918]
 To Search:
  • [simple_fifo] - verilog HDL original code a simple synch
File list (Check if you may need any files): 
sfifo.v

CodeBus www.codebus.net