Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: UART Download
 Description: VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly!
 Downloaders recently: [More information of uploader fangbin1990.ok]
 To Search:
File list (Check if you may need any files): 
新建 Microsoft Word 文档.doc

CodeBus www.codebus.net