Description: Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
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File list (Check if you may need any files):
myuart\db\myuart_14.asm.qmsg
......\..\myuart_14.asm_labs.ddb
......\..\myuart_14.cbx.xml
......\..\myuart_14.cmp.bpm
......\..\myuart_14.cmp.cdb
......\..\myuart_14.cmp.ecobp
......\..\myuart_14.cmp.hdb
......\..\myuart_14.cmp.kpt
......\..\myuart_14.cmp.logdb
......\..\myuart_14.cmp.rdb
......\..\myuart_14.cmp.tdb
......\..\myuart_14.cmp0.ddb
......\..\myuart_14.cmp2.ddb
......\..\myuart_14.cmp_merge.kpt
......\..\myuart_14.db_info
......\..\myuart_14.eco.cdb
......\..\myuart_14.eda.qmsg
......\..\myuart_14.fit.qmsg
......\..\myuart_14.hier_info
......\..\myuart_14.hif
......\..\myuart_14.lpc.html
......\..\myuart_14.lpc.rdb
......\..\myuart_14.lpc.txt
......\..\myuart_14.map.bpm
......\..\myuart_14.map.cdb
......\..\myuart_14.map.ecobp
......\..\myuart_14.map.hdb
......\..\myuart_14.map.kpt
......\..\myuart_14.map.logdb
......\..\myuart_14.map.qmsg
......\..\myuart_14.map_bb.cdb
......\..\myuart_14.map_bb.hdb
......\..\myuart_14.map_bb.logdb
......\..\myuart_14.pre_map.cdb
......\..\myuart_14.pre_map.hdb
......\..\myuart_14.rpp.qmsg
......\..\myuart_14.rtlv.hdb
......\..\myuart_14.rtlv_sg.cdb
......\..\myuart_14.rtlv_sg_swap.cdb
......\..\myuart_14.sgate.rvd
......\..\myuart_14.sgate_sm.rvd
......\..\myuart_14.sgdiff.cdb
......\..\myuart_14.sgdiff.hdb
......\..\myuart_14.sld_design_entry.sci
......\..\myuart_14.sld_design_entry_dsc.sci
......\..\myuart_14.syn_hier_info
......\..\myuart_14.tan.qmsg
......\..\myuart_14.tis_db_list.ddb
......\..\myuart_14.tmw_info
......\..\myuart_14_global_asgn_op.abo
......\..\prev_cmp_myuart_14.asm.qmsg
......\..\prev_cmp_myuart_14.eda.qmsg
......\..\prev_cmp_myuart_14.fit.qmsg
......\..\prev_cmp_myuart_14.map.qmsg
......\..\prev_cmp_myuart_14.qmsg
......\..\prev_cmp_myuart_14.tan.qmsg
......\incremental_db\compiled_partitions\myuart_14.root_partition.cmp.atm
......\..............\...................\myuart_14.root_partition.cmp.dfp
......\..............\...................\myuart_14.root_partition.cmp.hdbx
......\..............\...................\myuart_14.root_partition.cmp.kpt
......\..............\...................\myuart_14.root_partition.cmp.logdb
......\..............\...................\myuart_14.root_partition.cmp.rcf
......\..............\...................\myuart_14.root_partition.map.atm
......\..............\...................\myuart_14.root_partition.map.dpi
......\..............\...................\myuart_14.root_partition.map.hdbx
......\..............\...................\myuart_14.root_partition.map.kpt
......\..............\README
......\myuart_14.asm.rpt
......\myuart_14.done
......\myuart_14.dpf
......\myuart_14.eda.rpt
......\myuart_14.fit.rpt
......\myuart_14.fit.smsg
......\myuart_14.fit.summary
......\myuart_14.flow.rpt
......\myuart_14.map.rpt
......\myuart_14.map.summary
......\myuart_14.pin
......\myuart_14.pof
......\myuart_14.qpf
......\myuart_14.qsf
......\myuart_14.qws
......\myuart_14.sof
......\myuart_14.tan.rpt
......\myuart_14.tan.summary
......\myuart_14.v
......\myuart_14.v.bak
......\simulation\modelsim\myuart_14.sft
......\..........\........\myuart_14.vo
......\..........\........\myuart_14_modelsim.xrf
......\..........\........\myuart_14_v.sdo
......\speed_select.v
......\speed_select.v.bak
......\uart_rx.v
......\uart_rx.v.bak
......\uart_tx.v
......\uart_tx.v.bak
......\incremental_db\compiled_partitions
......\simulation\modelsim
......\db
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