VerilogUart\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf
...........\.........\....\...............\DESIGN_FIRMWARE.sdb
...........\.........\....\.......IO\DESIGN_IO.cxf
...........\.........\....\.........\DESIGN_IO.sdb
...........\.........\....\UartSmartDesign\datasheet.xsl
...........\.........\....\...............\drcss.xsl
...........\.........\....\...............\UartSmartDesign.cxf
...........\.........\....\...............\UartSmartDesign.sdb
...........\.........\....\...............\UartSmartDesign.v
...........\.........\....\...............\UartSmartDesign_DataSheet.xml
...........\.........\....\...............\UartSmartDesign_DRC.xml
...........\.........\....\...............\UartSmartDesign_manifest.txt
...........\..nstraint\UartSmartDesign_sdc.sdc
...........\designer\impl1\run_designer_tool.log
...........\........\.....\run_designer_tool.tcl
...........\........\.....\run_pinrpt.tcl
...........\........\.....\uart.ide_des
...........\........\.....\uart8n1.ide_des
...........\........\.....\UartSmartDesign.adb
...........\........\.....\................dtf\verify.log
...........\........\.....\UartSmartDesign.ide_des
...........\........\.....\UartSmartDesign.pdb
...........\........\.....\UartSmartDesign.pdb.depends
...........\........\.....\UartSmartDesign.tcl
...........\........\.....\UartSmartDesign_compile_log.rpt
...........\........\.....\UartSmartDesign_compile_report.txt
...........\........\.....\................fp\$$FlashPro_97574.L$$
...........\........\.....\..................\projectData\UartSmartDesign.pdb
...........\........\.....\..................\UartSmartDesign.pro
...........\........\.....\..................\UartSmartDesign.tcl
...........\........\.....\..................\UartSmartDesign_program.log
...........\........\.....\UartSmartDesign_fp.tcl
...........\........\.....\UartSmartDesign_globalnet_report.txt
...........\........\.....\UartSmartDesign_globalusage_report.txt
...........\........\.....\UartSmartDesign_iobank_report.txt
...........\........\.....\UartSmartDesign_maxdelay_timingviolations_report.txt
...........\........\.....\UartSmartDesign_maxdelay_timing_report.txt
...........\........\.....\UartSmartDesign_mindelay_timingviolations_report.txt
...........\........\.....\UartSmartDesign_mindelay_timing_report.txt
...........\........\.....\UartSmartDesign_placeroute_log.rpt
...........\........\.....\UartSmartDesign_place_and_route_report.txt
...........\........\.....\UartSmartDesign_prgdata_log.rpt
...........\........\.....\UartSmartDesign_report_pin_byname.txt
...........\........\.....\UartSmartDesign_report_pin_bynumber.txt
...........\........\.....\UartSmartDesign_timingconstraints_log.rpt
...........\........\.....\UartSmartDesign_verifytiming_log.rpt
...........\........\.....\UartTop.ide_des
...........\hdl\fifo8x15.v
...........\...\lowpass.v
...........\...\rst.v
...........\...\uart8n1_ctrl.v
...........\...\uart8n1_rx.v
...........\...\uart8n1_tx.v
...........\...\UartTop.v
...........\simulation\modelsim.ini
...........\..........\modelsim.ini.sav
...........\.martgen\DESIGN_FIRMWARE_work.ixf
...........\........\DESIGN_IO_work.ixf
...........\........\PLL_core\PLL_core.cxf
...........\........\........\PLL_core.gen
...........\........\........\PLL_core.log
...........\........\........\PLL_core.v
...........\........\PLL_core_work.ixf
...........\........\smartgen.aws
...........\........\UartSmartDesign_work.ixf
...........\.ynthesis\.recordref_modgen
...........\.........\backup\uart8n1.srr
...........\.........\......\UartSmartDesign.srr
...........\.........\dm\UartSmartDesign_comp.xdm
...........\.........\flatsch.srs
...........\.........\flatsch.sxr
...........\.........\run_options.txt
...........\.........\scratchproject.prs
...........\.........\stdout.log
...........\.........\sub___cin_w4.fdepxmr
...........\.........\.ynlog\constraint_check.rpt.rptmap
...........\.........\......\map.srr.rptmap
...........\.........\......\pre_map.srr.rptmap
...........\.........\......\report\uart8n1_compiler_errors.txt
...........