Search - 32 bit division

[Other resource] math8051

Description: A collection of math routines including 8-bit, 16-bit, 32-bit signed and unsigned addition, subtraction, multiplication, and division. Very nice code library with heavy in-line documentation! Been looking for multi-byte divide? Here it is. -A collection of math routines including 8-bit, 16-bit, 32-bit signed and unsigned addition, subtraction, multiplication, and division. Very nice code library with heavy in-line documentation! Been looking for multi-byte divide Here it is.
Platform: | Size: 4497 | Author: 驱逐倭寇 | Hits:

[Other resource] 除法32

Description: 基于５１单片机的３２位除法程序-based on the 32-bit microcontroller division procedures
Platform: | Size: 1354 | Author: 刘役 | Hits:

[SCM] 除法32

Description: 基于５１单片机的３２位除法程序-based on the 32-bit microcontroller division procedures
Platform: | Size: 1024 | Author: 刘役 | Hits:

[SCM] math8051

Description: A collection of math routines including 8-bit, 16-bit, 32-bit signed and unsigned addition, subtraction, multiplication, and division. Very nice code library with heavy in-line documentation! Been looking for multi-byte divide? Here it is. -A collection of math routines including 8-bit, 16-bit, 32-bit signed and unsigned addition, subtraction, multiplication, and division. Very nice code library with heavy in-line documentation! Been looking for multi-byte divide Here it is.
Platform: | Size: 4096 | Author: 驱逐倭寇 | Hits:

[VHDL-FPGA-Verilog] 200632146671689

Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
Platform: | Size: 741376 | Author: lele | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[Embeded-SCM Develop] Qdiv

Description: 使用移位减法完成32位除法操作。适用于没有除法指令的嵌入式处理器。源码简单，适用-Use of translocation to complete 32-bit subtraction division operation. Does not apply to the embedded processor division instruction. Source is simple, the application of
Platform: | Size: 1024 | Author: 10664417 | Hits:

[VC/MFC] MD5

Description: 在一些初始化处理后，MD5以512位分组来处理输入文本，每一分组又划分为16个32位子分组。算法的输出由四个32位分组组成，将它们级联形成一个128位散列值。首先填充消息使其长度恰好为一个比512位的倍数仅小64位的数。填充方法是附一个1在消息后面，后接所要求的多个0，然后在其后附上64位的消息长度（填充前）。这两步的作用是使消息长度恰好是512位的整数倍（算法的其余部分要求如此），同时确保不同的消息在填充后不相同。四个32位变量初始化为：-After treatment in a number of initialization, MD5 to 512 division to deal with input text, each sub-divided into 16 sub-32 seat. Algorithm output consists of four sub-groups, 32, cascade them to form a 128-bit hash value. First of all, it filled the news for a length of just over 512 in multiples of 64 only a few small. Filling method is attached to the back of a 1 in the message, followed by the required number of 0, and then subsequently attached to the message length of 64 (before filling). The role of these two steps so that messages are exactly the length of integer multiple of 512 (the rest of the algorithm requested the case), while ensuring that the different sources in the same after filling. Four 32-bit variable is initialized as follows:
Platform: | Size: 2048 | Author: 修凤志 | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] div(FLP)

Description: 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除-Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Platform: | Size: 18432 | Author: TTJ | Hits:

[Windows Develop] DNF

Description: DNF的召唤师挂机脚本说明： ======DNF简单召唤====== 比较适合懒的召唤师玩家简单介绍下：按F1-F8可以召唤出怪按F9可以使用冰补血（囧）按F10则停止（按着2~3秒吧） F11开始F12停止【作者介绍】就是你脚本附件：运行环境：分辨率：1440x900 色深：32位操作系统：Windows XP-DNF script hang up the call of the division Description: ====== DNF relatively easy fit ====== lazy call the call of the division of players easy introduction: According to F1-F8 to call the blame can be used by ice Buxue F9 (囧) were stopped by the F10 (according to you 2 ~ 3 second) F11 stop start F12】【author is your introduction attachment script: Run Environment: Resolution: 1440x900 Color Depth: 32-bit operating system: Windows XP
Platform: | Size: 1024 | Author: 毛毛 | Hits:

[VHDL-FPGA-Verilog] chengfaqi

Description: 乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
Platform: | Size: 5184512 | Author: 风清扬 | Hits:

[Other Embeded program] CPUsourcecode

Description: 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
Platform: | Size: 93184 | Author: 李敏 | Hits:

[uCOS] s1c33_uCos

Description: uCos在s1c33上的移植 S1C33 MCU EPSON最新的32位微处理器系列，专用于需要高级数据处理的便捷设备。 CPU性能核心CPU 精工EPSON32位的RISC CPU，32位内部数据处理 33MHz 105条16位固定长度的指令 16个32位多用途的寄存器在60MHZ操作下的最小指令执行时间为16.7ns 乘法、除法和MAC指令内存 0~128K ROM 8K RAM 片内周边电路晶振电路 32.769K~33MHz 定时器 8位6道 16位6道和带告警功能的时钟各1道计数器 4道，可选择时钟同步系统、异步系统、或IrDA接口 A/D转换 10位8通道 DMA 4道高速DMA 128道IDMA 通用 I/O 13位输入端口和29位I/O端口片内周边电路可编程时钟产生器 Prescaler 8位可编程定时器 6道 16位可编程定时器 6道时钟定时器 1道串口 4道 I/O端口 13位+29位 A/D转换器 ADC 直接存储器存取 DMA -S1C33 MCU EPSON latest 32-bit microprocessor series, dedicated to the convenience needs of advanced data processing equipment. CPU performance Seiko EPSON32 bit core CPU RISC CPU, 32-bit internal data processing 33MHz 105 16-bit fixed length instruction 16 multi-purpose 32-bit registers In 60MHZ operation, the minimum instruction execution time of 16.7ns Multiplication, division and the MAC Directive Memory, 0 ~ 128K ROM 8K RAM On-chip peripheral circuits 32.769K ~ 33MHz crystal oscillator circuit Timer 8 6 16 6 and clock with alarm function of each one Counter 4, optional clock synchronous system, asynchronous systems, or IrDA interfaces A/D converter 10-bit 8-channel DMA 4 道 high-speed DMA 128 道 IDMA Universal I/O 13-bit input ports and 29 I/O ports On-chip peripheral circuits Programmable Clock Generator Prescaler 8-bit programmable timer 6 16-bit programmable timer 6 Clock Timer 1 Serial 4 I/O port 13+29 bit A/D converter ADC Direct
Platform: | Size: 10240 | Author: dupeng | Hits:

[Algorithm] CRC-32

Description: CRC是由待傳輸的資料區塊計算出的，它的計算方式是將待傳輸的區塊視為一堆連續位元所構成的一整個數值，並將此數值除以一特定的除數，通常以二進位表示，此除數又稱為衍生多項式 (Generation Polynomial)，該除數一般皆由設計硬體或軟體的廠商所提供，而除數值位元數目則視欲得到的 CRC 位元數目而定。-CRC is transmitted by the data block to be calculated, which is calculated by the block to be transmitted as a continuous bit composed of a bunch of a whole value and this value divided by a particular divisor, usually binary, said that this division is also known as derivative polynomial (Generation Polynomial), the divisor rests general hardware or software design provided by the manufacturers, while the number of inter-bit value as the CRC bits to yield a depending on the number.
Platform: | Size: 275456 | Author: david | Hits:

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