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[Books] VLSI中文版_上.zip

Description: 目 錄 1 目 錄 Unix基本指令 第一章 zzzzzzzzzzzz 1.1 本章教學大綱...................................................1-2 1.2 Unix的歷史......................................................1-2 1.3 Unix基本指令簡介..........................................1-5 1.4 編輯器vi.........................................................1-45 1.5 Unix的基本檔案系統.....................................1-51 1.6 相關網站.........................................................1-60 1.7 課後習題相關網站.........................................1-61 CMOS VLSI設計概念與Design Flow 第二章 zzzzzzzzzzzz 2.1 本章教學大綱...................................................2-2 2.2 IC的各種設計方法..........................................2-2 2.3 MOS電晶體....................................................2-10 2.4 CMOS的技術.................................................2-16 2.5 Bottom Up與Top Down設計........................2-25 2.6 Full Custom IC的設計流程............................2-29 2.7 Design Frame work II之檔案結構..................2-33 2.8 CAD/CAE軟體的資料格式標準....................2-40 2.9 國科會晶片實現中心 ( CIC )........................2-42 2.10 作業.................................................................2-44 2 目 錄 第 如何進入Cadence 三章 zzzzzzzzzzzz 3.1 如何進入Cadence.............................................3-2 3.2 如何將Cadence 4.3.X的Lib轉成OPUS-97A 4.4版的Lib......................................................3-4 3.3 建立新的Library............................................3-12 3.4 建立新的cellview...........................................3-17 Schematic 第四章 zzzzzzzzzzzz 4.1 Schematic 指令介紹.......................................4-2 4.2 Schematic繪圖視窗選項介紹..........................4-3 4.3 實作範例：建立一Buffer的Schematic View4-27 4.4 將Schematic View轉出網路檔 (netlist) 的CDL out...................................................................4-30 Symbol 第五章 zzzzzzzzzzzz 5.1 Symbol View快速選擇介紹.............................5-2 5.2 Symbol繪圖視窗選擇項介紹...........................5-4 5.3 實作範例：建立一Buffer的Symbol View...5-22 Layout 第六章 zzzzzzzzzzzz 6.1 Layout View......................................................6-2 6.2 Layer Selection Window (LSW) 視窗..............6-3 6.3 Layout快速選項列介紹...................................6-3 6.4 Layout View繪圖視窗選擇項介紹..................6-6 6.5 實作範例：建立一Buffer的Layout View....6-37 目 錄 3 第 Dracula 七章 zzzzzzzzzzzz 7.1 Dracula介紹.....................................................7-2 7.2 DRC(Design Rule Checking).............................7-2 7.3 DRC錯誤範例說明........................................7-15 7.4 DRC Error Message.........................................7-24 7.5 ERC錯誤範例說明.........................................7-27 7.6 LVS(Layout vs. Schematic Check)..................7-32 7.7 LVS錯誤範例說明.........................................7-49 7.8 LVS的錯誤型態.............................................7-62 7.9 LPE(Layout Parameter Extraction)..................7-78 I/O Circuit及Package 第八章 zzzzzzzzzzzz 8.1 I/O Circuit概述.................................................8-2 8.2 基本分類...........................................................8-4 8.3 CIC之I/O PAD................................................8-9 8.4 I/O PAD的規劃..............................................8-28 8.5 範 例.............................................................8-34 8.6 包裝 (Package)...............................................8-36 SPICE Simulation 第九章 zzzzzzzzzzzz 9.1 本章教學大綱...................................................9-2 9.2 SPICE Simulation的基本概念..........................9-2 9.3 SPICE的語法...................................................9-5 9.4 用HSPICE來模擬............................................9-8 9.5 用PSPICE來模擬..........................................9-53 9.6 用IsSPICE來模擬..........................................9-58 9.7 用SBTSPICE來模擬.....................................9-68 4 目 錄 第 Design Guide 十章 zzzzzzzzzzzz 10.1 本章教學大綱.................................................10-2 10.2 Design for Reliability......................................10-2 10.3 Design for Testability....................................10-27 範例：JK FF 第十一章 zzzzzzzzzzzz 11.1 本章教學大綱.................................................11-2 11.2 JK正反器電路圖............................................11-2 11.3 建立所有的邏輯閘.........................................11-3 11.4 JK正反器之schematic及symbol view........11-10 11.5 用HSPICE來模擬JK正反器之狀態輸出...11-11 11.6 Debug............................................................11-16 11.7 PDRACULA的驗證.....................................11-29 教育性晶片製作申請程序及範例 附錄一 Design Rules實例 (Mead & Conway) 附錄二 XV使用說明 附錄三 將電路加入IOPAD的方法 附錄四 加入IOPAD的幾個動作 附錄五 積體電路電路布局保護法 附錄六 參考資料
Platform: | Size: 9318659 | Author: g9676612@cycu.edu.tw | Hits:

[SourceCode] CIC滤波器matlab代码

Description: CIC滤波器matlab代码 D=5; r=D; fs=1e5; S3_cic=conv(conv(ones(1,D),ones(1,D)),ones(1,D)); %三个单级卷积 [h3,f3]=freqz(S3_cic,1,1000,fs); plot(f3/(fs/2),20*log10(abs(h3))-max(20*log10(abs(h3))),'r','LineWidth',1.4) ylabel('\fontsize{12}\bf幅度响应（dB）') xlabel('\fontsize{12}\bf归一化频率(\times\pi rad/sample)') grid; box on; axis([0 1 -80, 0])
Platform: | Size: 680 | Author: 530228758@qq.com | Hits:

[VHDL-FPGA-Verilog] c19_CICfilter

Description: 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
Platform: | Size: 1024 | Author: 李平 | Hits:

[source in ebook] cic512

Description: 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证，一、具有很高的速率-5-order CIC filter, collected 12 times the Verilog procedures are by simulation, one with a very high rate
Platform: | Size: 1024 | Author: xiebin | Hits:

[Other] xugc

Description: cic512 5阶cic滤波器，抽取12倍，的verilog程序，已经通过仿真验证 -5CIC
Platform: | Size: 1024 | Author: 黄锦港 | Hits:

[DSP program] CIC6_fir_comp_mlab

Description: CIC补偿滤波器设计，CIC滤波器采用5阶6倍抽取设计。-CIC compensation filter design, CIC filter 5 samples 6 times the design stage.
Platform: | Size: 2048 | Author: 42200306 | Hits:

[DSP program] CIC8_fir_comp_mlab

Description: CIC抽取补偿滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC compensation filter design samples, CIC filter order of 8 times 5 samples.
Platform: | Size: 2048 | Author: 42200306 | Hits:

[DSP program] CIC4_fir_comp_mlab

Description: CIC抽取补偿滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC compensation filter design samples, CIC filter order 4 times using 5 samples.
Platform: | Size: 2048 | Author: 42200306 | Hits:

[VHDL-FPGA-Verilog] CIC_DEC

Description: CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
Platform: | Size: 1024 | Author: 42200306 | Hits:

[VHDL-FPGA-Verilog] CIC_DEC_3

Description: CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
Platform: | Size: 1024 | Author: 42200306 | Hits:

[VHDL-FPGA-Verilog] CIC_DEC_4

Description: CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
Platform: | Size: 1024 | Author: 42200306 | Hits:

[VHDL-FPGA-Verilog] CIC_DEC_6

Description: CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
Platform: | Size: 1024 | Author: 42200306 | Hits:

[matlab] cic5

Description: matlab CIC滤波器程序,5级CIC滤波器的设计,采用优化结构，采样速率在积分器后降低；-matlab CIC program,five taps design.
Platform: | Size: 1024 | Author: 石乐 | Hits:

[VHDL-FPGA-Verilog] cic

Description: 在MATLAB2007A/SIMULINK环境下用DSP BUILDER8.0实现了五级CIC，解决了溢出问题。生成了可用的VHDL文件。- DSP BUILDER8.0 A 5 stages CIC filer is realized in MATLAB2007A/SIMULINK by using DSP Builder 8.0.The overflow problem is resulved.Useful VHDL files are generated at last.
Platform: | Size: 1543168 | Author: hcq | Hits:

[Wavelet] 123

Description: matlab实现的多相滤波器，cic抽取D=5时例子，及级联型的cic的程序。-matlab implementation of the polyphase filter, cic examples taken D = 5 时, and the cascade of cic procedures.
Platform: | Size: 1024 | Author: allen | Hits:

[VHDL-FPGA-Verilog] cic5

Description: 5级级联CIC滤波器的VHDL程序。CIC是最简单最易实现的低通滤波器，通常CIC滤波器如果采用单级，带外衰减不够，因此需要级联使用，5级级联的CIC带外衰减能够满足大多数的设计要求。而带内的衰减可以采用补偿滤波器抵消掉绝大部分。-the code of 5-CIC
Platform: | Size: 1024 | Author: 陈建敏 | Hits:

[VHDL-FPGA-Verilog] cic_filter

Description: 5阶cic滤波器 使用vdhl编写 下载后将tb代码烤出 新建，然后综合仿真！-5 cic filter using vdhl written order to download the code will tb baked New, and then integrated simulation!
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA_CIC

Description: 用Count计数法实现5级CIC滤波器，能够提前或者延迟一个周期采样。能综合-Implementation level 5 CIC filter with Count counting method, one can advance or delay the sampling period.
Platform: | Size: 1024 | Author: lihe | Hits:

[Communication-Mobile] CIC_desgin

Description: 1）设计不同长度的单级CIC滤波器，并plot出阶数为2、5、7、8的CIC滤波器幅频特性 2）设计出5级CIC滤波器(1) design a single level CIC filter with different lengths, and the amplitude frequency characteristics of the plot order of 2, 5, 7, 8 of the CIC filter 2) a 5 level CIC filter is designed)
Platform: | Size: 1024 | Author: 吴简 | Hits:

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