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[
VHDL-FPGA-Verilog
]
74hc74
Description:
带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
Platform:
|
Size:
316416
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Author:
mypudn0001
|
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