Search - DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: 基于NIOS II的电视视频处理工程文件，很完整。-NIOS II on TV video processing project file, it is complete.
Platform: | Size: 163840 | Author: 高天天 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: 基于FPGA的视频转化的I2c配置芯片解码模块和解交织模块-FPGA-based video conversion reconciliation I2c configuration chip interleaving block decoding module
Platform: | Size: 713728 | Author: 小锋 | Hits:

[Streaming Mpeg4] DE2_70_TV

Description: 这个是DE2_70_TV的例子，把原先的NTSC显示改成了PAL显示，可惜网上没找到具体的说明文档，有些细节还要靠自己专研，总之，靠老师同学朋友都会浪费时间，靠自己才是保险的，虽然慢。-This is DE2_70_TV example, the display changed the original NTSC PAL displays, but unfortunately could not find a specific online documentation, and some details have to rely on themselves specializes in short, their teachers, classmates and friends are a waste of time, is the insurance on their own , though slowly.
Platform: | Size: 5173248 | Author: 杨兔艳 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: YUV 信号转化为RGB 色彩信号。采用SDRAN, 将色差信号转化为为电视VGA信号。-yuv signal convert to RGB signal
Platform: | Size: 6342656 | Author: wang yong | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: Verilog，DE2-70 TV范例，视频解码-An Example of convert dvd to video display moniter for DE2-70 in verilog
Platform: | Size: 4995072 | Author: 唐小飞 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV_sobel.7

Description: DE2_70_TV與DE2_70_D5M_LTM的架構非常類似，都是以SDRAM當做frame buffer，所以若要加上演算法，基本上也是放在SDRAM之前做前處理，或者放在SDRAM之後做後處理。-The architecture DE2_70_TV and DE2_70_D5M_LTM very similar, as a frame buffer, so coupled with the algorithm to, basically on the SDRAM before doing the pre-treatment or post-processed on the SDRAM to SDRAM.
Platform: | Size: 71680 | Author: 林生 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: de2 70 开发板的演示程序，verilog语言编写，视频输入输出-de2 70 development board demo program, verilog language written, video input and output
Platform: | Size: 181248 | Author: chris | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: NTSC视频经过处理转化VGA，不需要进行编程，只需要把硬件电路接好即可-NTSC CONVERTS INTO VGA
Platform: | Size: 5813248 | Author: 徐春辉 | Hits:

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[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

[Streaming Mpeg4] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV_sobel.7

[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] DE2_70_TV

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