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[Communication] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通
Platform: | Size: 148330 | Author: 鲁东旭 | Hits:

[ELanguage] LUTFPGA

Description: 一种LUT函数运算单元的FPGA实现方法，希望能够帮助大家
Platform: | Size: 60836 | Author: 张治邦 | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[ELanguage] LUTFPGA

Description: 一种LUT函数运算单元的FPGA实现方法，希望能够帮助大家-A LUT function FPGA computing modules to achieve, and I hope that can help you
Platform: | Size: 60416 | Author: 张治邦 | Hits:

[VHDL-FPGA-Verilog] HwLog10

Description: 用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
Platform: | Size: 13312 | Author: vincent | Hits:

[VHDL-FPGA-Verilog] DPD_LUT

Description: 一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT
Platform: | Size: 2561024 | Author: 智慧川 | Hits:

[VHDL-FPGA-Verilog] FPGA_LUT

Description: 基于FPGA的大规模查找表设计与实现,对大规模查找表设计有一定帮助-Large-scale look-up table-based FPGA design and implementation of large-scale look-up table design will help
Platform: | Size: 273408 | Author: jh | Hits:

[VHDL-FPGA-Verilog] rom--mif

Description: 生成fpga的rom查找表的c语言和matlab程序还有一个生成正弦和余弦mif文件的生成器-fpga rom lut
Platform: | Size: 134144 | Author: liuheshan | Hits:

[VHDL-FPGA-Verilog] MEMORIA_LUT

Description: THIS CODE SHOWS HOW TO USE THE LUT IN A SPARTAN FPGA AS MEMORY.
Platform: | Size: 1024 | Author: Cian | Hits:

[Other] da_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） ​ 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。​ 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能，采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA)，将MAC运算转化为查找表(Look-Up-Table, LUT)输出，不仅能在硬件规模上得到改善，而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器，并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[VHDL-FPGA-Verilog] 1-D-DWT_verilog-code

Description: Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform. -Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.
Platform: | Size: 1474560 | Author: jeason | Hits:

[VHDL-FPGA-Verilog] jishuqi

Description: FPGA应用底层开发的逻辑单元slice连线实现计数器的功能，包含代码及仿真(FPGA applies the logic unit slice connection that is developed at the bottom to realize the function of counter, including code and simulation.)
Platform: | Size: 6642688 | Author: ltfy咖啡 | Hits:

[Graph program] DWT_verilog-code

Description: 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
Platform: | Size: 1473536 | Author: asde198250 | Hits:

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