Search - QuartusII6

[Other resource] quartusII_clock

Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
Platform: | Size: 7180017 | Author: 河南 | Hits:

[Embeded-SCM Develop] QuartusII6.0_ppt

Description: QuartusII6.0的英文培训资料277页的ppt宝贵资料，图文并茂，一步步教你使用Quartus
Platform: | Size: 4632711 | Author: 王晓 | Hits:

[Other resource] multi-wave-creator

Description: 基于FPGA的多波形发生器（编程环境QuartusII6.0）
Platform: | Size: 1054120 | Author: 朱旋风 | Hits:

[Other resource] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。
Platform: | Size: 233023 | Author: 余宾客 | Hits:

[Other resource] SCI

Description: VHDL写的SCI接口。quartusII6.0的工程！
Platform: | Size: 195916 | Author: sunhao | Hits:

[DSP program] quartusII_clock

Description: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
Platform: | Size: 7562240 | Author: 河南 | Hits:

[Embeded-SCM Develop] QuartusII6.0_ppt

Description:
Platform: | Size: 4632576 | Author: 王晓 | Hits:

[VHDL-FPGA-Verilog] multi-wave-creator

Description: 基于FPGA的多波形发生器（编程环境QuartusII6.0）-FPGA-based Multi-Waveform Generator (programming environment QuartusII6.0)
Platform: | Size: 1053696 | Author: 朱旋风 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] SCI

Description: VHDL写的SCI接口。quartusII6.0的工程！-SCI interface written in VHDL. quartusII6.0 works!
Platform: | Size: 195584 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] dds

Description: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Platform: | Size: 105472 | Author: xx | Hits:

[VHDL-FPGA-Verilog] NiosII_clock

Description: 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
Platform: | Size: 378880 | Author: 王磊 | Hits:

[Documents] QuartusII6[1].0shiyong

Description: Quartus 视频教程短短不到十分钟学会Quaruts-A short video tutorial Quartus less than 10 minutes Quaruts Society
Platform: | Size: 7004160 | Author: guhaitao | Hits:

[VHDL-FPGA-Verilog] rom

Description: 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
Platform: | Size: 1024 | Author: 干璐 | Hits:

[VHDL-FPGA-Verilog] sram64

Description: 随机存储器VHDL代码，已用quartusII6.0验证，可用，可实现模块-Random access memory VHDL code has been used to verify quartusII6.0 can be used to deliver modules
Platform: | Size: 2048 | Author: 干璐 | Hits:

[VHDL-FPGA-Verilog] butterfly

Description: 另一种蝶形运算的代码，可用quartusII6.0运用-A butterfly operation of the code, the use of available quartusII6.0
Platform: | Size: 3072 | Author: 干璐 | Hits:

[VHDL-FPGA-Verilog] LCD1602Display

Description: FPGA中LCD1602驱动开发设计，软件quartusII6.0，verilog-LCD1602 driver in the development of FPGA design, software quartusII6.0, verilog
Platform: | Size: 365568 | Author: 张一 | Hits:

[VHDL-FPGA-Verilog] ps2_keyboard

Description: FPGA PS2键盘驱动设计，使用软件QuartusII6.0 verilog-FPGA PS2 keyboard-driven design, the use of software QuartusII6.0 verilog
Platform: | Size: 832512 | Author: 张一 | Hits:

[Other Embeded program] QuartusII6.0

Description: 是QuartusII6.0使用步骤视频，很实用，很方便，用时不多但效率高-Is the use of steps QuartusII6.0 video, very practical, very convenient to use, when a small but efficient
Platform: | Size: 7049216 | Author: ring | Hits:

[VHDL-FPGA-Verilog] QuartusII6.0_cn

Description: QuartusII6.0简体中文教程.pdf，讲的很详细，共有260页，很好的资料-QuartusII6.0 English tutorial. Pdf, said very detailed, 260 pages, very good information
Platform: | Size: 2068480 | Author: yang | Hits:

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[Other resource] quartusII_clock

[Embeded-SCM Develop] QuartusII6.0_ppt

[Other resource] multi-wave-creator

[Other resource] clock

[Other resource] SCI

[DSP program] quartusII_clock

[Embeded-SCM Develop] QuartusII6.0_ppt

[VHDL-FPGA-Verilog] multi-wave-creator

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] SCI

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] NiosII_clock

[Documents] QuartusII6[1].0shiyong

[VHDL-FPGA-Verilog] rom

[VHDL-FPGA-Verilog] sram64

[VHDL-FPGA-Verilog] butterfly

[VHDL-FPGA-Verilog] LCD1602Display

[VHDL-FPGA-Verilog] ps2_keyboard

[Other Embeded program] QuartusII6.0

[VHDL-FPGA-Verilog] QuartusII6.0_cn

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