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Description: SKY 通用传奇登陆器(音乐拍卖)源码，可执行，编译。
-SKY universal legend landers (music auction) source code, executable, compiler.
Platform: |
Size: 5065728 |
Author: 十三妖 |
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Description: 非常抱歉，上次发布前由于我这里网络的问题，测试飞信的登录过程没有问题，现在才发现登录过程有问题，因此对登录过程进行了修正，请下载这个新版本的GreenFetion，请站长帮忙更新或者把上一个版本的删除，见谅！
软件名称：Delphi版飞信GreenFetion源码
开发环境：WindowsXP,Delphi2007
三方控件：Indy9（Delphi自带）
说明:
Delphi盒子(www.2ccc.com)首发。
参考Php版飞信（http://sourceforge.net/projects/openfetion/）用Delphi实现了中国移动飞信2008协议的登录和发短信部分。其它功能并没有实现，不过在此基础上实现起来应该没有难度。
该程序为纯绿色软件，不写注册表，无需Dll文件和配置文件。
程序中用到的SHA1算法源码和TIEHttp控件均来源于网络，感谢二位作者。
使用之前请先注册一个飞信号。
参考资料:
1: 飞信协议分析， http://hi.baidu.com/nathan2007/blog/category/％B7％C9％D0％C5％D0％AD％D2％E9％B7％D6％CE％F6
2: Php版飞信(http://sourceforge.net/projects/openfetion/，已经附加在根目录下，文件名是fetion.php-err
Platform: |
Size: 546816 |
Author: jkjkjk |
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Description: 摘要书法SHA1的实现，自己做的 比较简单
将算法的内容封装d-Abstract Calligraphy SHA1 implementation of their own will to do the relatively simple algorithm for the content of package dll
Platform: |
Size: 2243584 |
Author: yushijun |
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Description: sha1_testbench.v
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.-sha1_testbench.v
-- Testbench with vectors NIST FIPS 180-2
sha1_exec.v
-- Top level sha1 module
sha1_round.v
-- primitive sha1 round
dffhr.v
-- generic parameterizable D-flip flop library
Performance Analysis
Performance equation of core is
frequency in MHz * (512bits/block) / (81 rounds/block). The
cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7
FPGA which results in 700 Mbps processing rate.
Note: This calculation ignores the effect of a partially full
last block
Finally, Padding, HMAC, and bus interface functionality is not
provided. These will vary with the particular system design.
The core size is about 800 Xilinx Virtex II FPGA Family Slices.
I welcome feedback on any aspects of this design.
Platform: |
Size: 6144 |
Author: sam |
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