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[VHDL-FPGA-Verilog] sdh

Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Platform: | Size: 6144 | Author: liu | Hits:

[VHDL-FPGA-Verilog] pcm1804_i2s_data_adjust2

Description: 用于pcm1804调整I2S的数据，使I2S的音频同步并且在FIFO中不溢出。能够自动判断FIFO --中的状态，通过调整从FIFO中输出的数据的个数来使FIFO既不上溢也不下溢。 -- 为了达到更高的精度要求，可以通过加大采样时钟clk的频率。-I2S for pcm1804 adjusted data, so that I2S audio synchronization and FIFO does not overflow. Can automatically determine the FIFO- the state, by adjusting the output from the FIFO in the number of data in order to make the FIFO does not overflow or underflow.- In order to achieve higher precision, you can increase the sampling clock frequency of clk.
Platform: | Size: 2048 | Author: WQL | Hits:

[VHDL-FPGA-Verilog] fifo_sync

Description: 脉冲同步电路,简单修改就可以使用,很使用的.-Pulse synchronization circuit, a simple modification you can use, it is used.
Platform: | Size: 1024 | Author: | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[SCM] 1

Description: 本设计采用Cypress公司支持USB2.0协议标准的EZ-USB FX2系列之CY7C68013芯片作为帧同步信号发送器的USB接口芯片，在uVision2开发环境下利用Keil C51完成了满足帧同步信号发送器基本要求的固件设计，具体采用了批量传输方式、大端点三缓冲设置、定时器中断方式的同步脉冲和数据的发送、软FIFO方式数据存放以及I2C总线下的LED显示等技术，最后协助编写USB底层驱动程序实现了固件自动下载。经过测试，所设计的帧同步信号发送器基本达到了课题所要求的基本原理性设计与验证。 -This design uses Cypress supports USB2.0 protocol standards of EZ-USB FX2 Series CY7C68013 chip as a frame synchronization signal transmitter of the USB interface chip, in uVision2 development environment using Keil C51 completed a frame synchronization signal to meet the basic requirements of transmitter firmware design, specific use of a bulk transfer mode, the endpoint buffer three settings, the timer interrupt the sync pulse and data transmission, soft FIFO mode and the I2C bus data repository under the LED display technology, assist in the preparation of the final bottom USB driver to achieve the firmware is automatically downloaded. After testing, the design of frame synchronization signal transmitter basic subjects required to achieve the basic principles of design and verification.
Platform: | Size: 603136 | Author: xmuyfng | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[Program doc] vhdlfi

Description: fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
Platform: | Size: 3072 | Author: lee | Hits:

[OS Develop] asynFifo

Description: 异步fifo在IC设计中，非常重要；是异步时钟域同步方法-Asynchronous fifo in IC design, is very important are asynchronous clock domain synchronization
Platform: | Size: 1024 | Author: leng | Hits:

[OS Develop] FIFO

Description: FIFO以及跨时钟域的同步问题。 FIFO有分离的地址总线和用以读写数据的数据通道，以及指示堆栈状态（满、将满等）的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be full, etc.) of the state line.
Platform: | Size: 3072 | Author: isaac | Hits:

[VHDL-FPGA-Verilog] sfifo

Description: verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] mypro_synfifo

Description: 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
Platform: | Size: 1275904 | Author: Hurley | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 这是本人学习FPGA时亲自原创的代码，实现的是8x8的fifo结构，采用同步的FIFO结构，仿真测试已经成功！-This is I learn when the original code FPGA in person, the realization of 8 x8 is the fifo structure, the synchronization of the fifo structure, the simulation test is a success!
Platform: | Size: 563200 | Author: xie hao | Hits:

[VHDL-FPGA-Verilog] vhdl_text3

Description: 设计一个数据宽度8bit，深度是16的 同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz， 将1－16连续写入FIFO，写满后再将其读出来（读空为止）。 仿真上述逻辑的时序-Design a data width 8bit depth of 16 the synchronization FIFO (read and write with the same clock), EMPTY, FULL output flag. Requirements FIFO read and write clock frequency of 20MHz, to 1-16 consecutive write FIFO, and then filled it read out (read empty so far). Timing simulation above logic
Platform: | Size: 6144 | Author: jiange | Hits:

[VHDL-FPGA-Verilog] AN66806

Description: 提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码-Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code
Platform: | Size: 110592 | Author: 胡小刚 | Hits:

[Shot Game] FIFO

Description: 同步fifo，能够实现同步的缓冲，希望对大家有用-Synchronous fifo, to achieve synchronization of the buffer, the hope that useful
Platform: | Size: 478208 | Author: 曾小猫 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 同步fifo和异步fifo程序，含时钟同步。运用格雷码-Synchronous FIFO and asynchronous FIFO FIFO procedures, including clock synchronization. Application of gray code
Platform: | Size: 2048 | Author: zhaohongbing | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO是通过时钟来确定是同步还是异步的，同步FIFO的读写操作是通用一个时钟来控制的。另一方面。两个不同频率或者不同香味的时钟来控制异步FIFO的读写操作。 异步FIFO 跨越时钟域的同步问题-FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other hand. Two different frequencies or different flavor to control the clock asynchronous FIFO read and write operations. FIFO asynchronous clock domain crossing synchronization issues
Platform: | Size: 3072 | Author: Isabelle Cheung | Hits:

[VHDL-FPGA-Verilog] syn_dp_fifo.v

Description: 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
Platform: | Size: 1024 | Author: junkaizhan | Hits:

[Other] fifo

Description: 学习Clifford_E论文之后完成的异步FIFO，可以完成异步时钟下的数据同步(After learning Clifford_E paper, the asynchronous FIFO can be completed under asynchronous clock data synchronization)
Platform: | Size: 2048 | Author: WWYMM | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Platform: | Size: 2048 | Author: wt2110 | Hits:
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