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Search - VHDL for JK FLIP FLOP

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[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[Other] vhdlcodes

Description: with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this site also.i really needed codes please accept that as soon as possible.
Platform: | Size: 2048 | Author: nitin | Hits:

[Other] jk-ff

Description: j-k flip flop implementation in XCS2-j-k flip flop implementation in XCS200
Platform: | Size: 15360 | Author: Amirali | Hits:

[VHDL-FPGA-Verilog] vhdl_jk

Description: 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
Platform: | Size: 201728 | Author: 刘轶龙 | Hits:

[ELanguage] 5

Description: Code for JK flip flop and SR flip flop
Platform: | Size: 1024 | Author: D S Manjunath | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
Platform: | Size: 1024 | Author: 龚成 | Hits:

[VHDL-FPGA-Verilog] jkandTflipflop

Description: this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. -this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 82944 | Author: jatab | Hits:

[Software Engineering] Jkflipflop

Description: it s a vhdl code for jk flip flop in vhdl
Platform: | Size: 6144 | Author: lavish | Hits:

[FlashMX] count10

Description: 十进制计数器 自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
Platform: | Size: 106496 | Author: liu jian ming | Hits:

[VHDL-FPGA-Verilog] jk

Description: 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
Platform: | Size: 291840 | Author: 宋茜 | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-jk-flip-flop

Description: vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
Platform: | Size: 11264 | Author: nasimus | Hits:

[assembly language] VHDL

Description: 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and computing method for the preparation of the 290 counter: Another compilation Act LS290 8 line decoder can end line without eight JK flip-flop election with a number of selector: full adder CASE statement:
Platform: | Size: 7168 | Author: Lynn | Hits:

[VHDL-FPGA-Verilog] jkchufaqi

Description: 此程序是根据jk触发器的功能用VHDL语言描写的jk触发器，供同学们学习交流-This program is based on the jk flip-flop functions with VHDL description jk flip-flop for students learning exchanges
Platform: | Size: 110592 | Author: 魏银玲 | Hits:

[Other] new_jk

Description: this a vhdl code for jk flip-flop-this is a vhdl code for jk flip-flop
Platform: | Size: 87040 | Author: mahzad | Hits:

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