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[Other resource] pingpufx

Description: 本设计以凌阳16位单片机SPCE061A为核心控制器件，配合Xilinx Virtex-II FPGA及Xilinx公司提供的硬件DSP高级设计工具System Generator，制作完成本数字式外差频谱分析仪。前端利用高性能A/D对被测信号进行采集，利用FPGA高速、并行的处理特点，在FPGA内部完成数字混频，数字滤波等DSP算法。
Platform: | Size: 258459 | Author: 郑坤 | Hits:

[Other resource] pwm1

Description: xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。
Platform: | Size: 79450 | Author: haolj | Hits:

[Other resource] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3688067 | Author: fuhao | Hits:

[matlab] 13lab03

Description: 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
Platform: | Size: 308224 | Author: zhangxing | Hits:

[Other] lab2ppc

Description: 嵌入式文档：Xilinx EDK 实验教程3： Adding Custom IP to an Embedded System Lab:-Embedded Document : Xilinx EDK three experimental Guide : Adding Custom IP to an Embedded System Lab :
Platform: | Size: 2028544 | Author: Lincker | Hits:

[Technology Management] 06626_DLL

Description: XILINX的DLL的使用介绍，对于时钟的应用有很大的帮助-XILINX the use of the DLL, the application for the clock will be very helpful
Platform: | Size: 1009664 | Author: fei0318 | Hits:

[VHDL-FPGA-Verilog] pwm1

Description: xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。-Xilinx design and complete a 10-bit D/F converter, the digital input from the keys K1, K2 to regulate, including the completion of plus 1 functions K1, K2 and completed by 1 functions, and to convert the structure of the West Oh F BUZZ crown to the buzzer on.
Platform: | Size: 79872 | Author: haolj | Hits:

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[VHDL-FPGA-Verilog] Xinlinx_footprint

Description: FPGA的部分封装图，可以为大家省下不少功夫。-FPGA part of package plans, we can save everyone a lot of kung fu.
Platform: | Size: 467968 | Author: raowei | Hits:

[DSP program] EMIF_COM

Description: 实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口-the interface for TI DSP and Xilinx s FPGAs
Platform: | Size: 1147904 | Author: 贺冲 | Hits:

[3G develop] src

Description: DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
Platform: | Size: 60416 | Author: youker | Hits:

[Other] DUC

Description: 基于软件无线电的SFF平台，采用Xilinx System Generator实现的数字上变频器-SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter
Platform: | Size: 53248 | Author: 刘荣毅 | Hits:

[Other] jj

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Platform: | Size: 546816 | Author: 黄奇家 | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] DCM

Description: xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Platform: | Size: 2599936 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] digital-storage-oscilloscope

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形-The problem to design a digital storage oscilloscope, to Xilinx, Inc. 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, the internal trigger, A/D converter, D/A conversion and I/O modules) using VHDL language programming, the arbitrary waveform
Platform: | Size: 14336 | Author: Jasen | Hits:

[VHDL-FPGA-Verilog] ADC

Description: xilinx spartan 3e上的A/D转换程序-xilinx spartan 3e A/D conversion process
Platform: | Size: 11264 | Author: 梁俊峰 | Hits:

[VHDL-FPGA-Verilog] async_reset_dff

Description: 异步复位的D触发器 vhdl fpga xilinx spartan-3e-D flip flop async-reset vhdl fpga xilinx spartan-3e
Platform: | Size: 914432 | Author: 朱飞亚 | Hits:

[Other] 使用 EMIF 将 Xilinx FPGA 与 TI DSP 平台接口

Description: 使用 EMIF 将 Xilinx FPGA 与 TI DSP 平台接口(D:\bootstrap\ce8c548c2a73a823101bfd000ce9d9e3)
Platform: | Size: 669696 | Author: xxyyzz0 | Hits:

[VHDL-FPGA-Verilog] SN7474

Description: 74LS74芯片行为级代码，实现了双D触发器与逻辑延迟，可利用modelsim仿真(74LS74 chip behavior level code)
Platform: | Size: 575488 | Author: superEason | Hits:
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