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[
VHDL-FPGA-Verilog
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xapp514_aes3-audio
Description:
DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
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4483072
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Author:
dcshl
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Search - aes_rx aes_crc xapp1014.zip
Search - aes_rx aes_crc xapp1014.zip