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[VHDL-FPGA-Verilog] fpga1394

Description: 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
Platform: | Size: 3072 | Author: 吴才路 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
Platform: | Size: 93184 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] dianzizhong

Description: 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
Platform: | Size: 550912 | Author: 刘恒辉 | Hits:

[ARM-PowerPC-ColdFire-MIPS] embedded_risc

Description: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Platform: | Size: 128000 | Author: 箫勇天 | Hits:

[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[VHDL-FPGA-Verilog] simple_fifo

Description: verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Platform: | Size: 1024 | Author: zxz | Hits:

[VHDL-FPGA-Verilog] ycrcb_rgb

Description: YUV转RGB的源程序，使用到了硬件加速器，可利用FGPA的乘法器加速处理速度。-YUV to RGB source, the use of a hardware accelerator, FGPA can be used to speed up the processing speed multiplier.
Platform: | Size: 107520 | Author: cloud | Hits:

[Embeded-SCM Develop] dualportRAM

Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Platform: | Size: 90112 | Author: 王雪松 | Hits:

[VHDL-FPGA-Verilog] 8251

Description: 8251的完整的功能的实现,可以进行编译,综合.-8251 complete function of the realization can be compiled and integrated.
Platform: | Size: 1393664 | Author: 田宇 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mem_ctrl.tar

Description: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Platform: | Size: 331776 | Author: youjia | Hits:

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] gpio

Description: 这是一个通用可编程接口的Verilog代码，可以设置触发条件，设置为电平方式、边沿方式。可以屏蔽不用的口。-This is a general programmable interface Verilog code, you can set a trigger condition is set to level the way the edge of the way. Can not shield the mouth.
Platform: | Size: 9216 | Author: kristing | Hits:

[VHDL-FPGA-Verilog] 8259

Description: 这是一个中断控制器的IP，功能很全，可以直接使用，类似于INTEL的8259，作为中断扩展。-This is an interrupt controller of the IP, is the whole function can be used directly, similar to INTEL in 8259, as extended interruption.
Platform: | Size: 2048 | Author: kristing | Hits:

[Other Embeded program] SRAMCotroller

Description: 一个SRAM控制器的IP核，很不错，有兴趣的朋友可以下去-An SRAM controller IP core, very good friends who are interested can go on
Platform: | Size: 322560 | Author: liufanyu | Hits:

[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:

[VHDL-FPGA-Verilog] can

Description: can总线的verilog设计与实现，很好的资料哦-the implention of can bus with verilog
Platform: | Size: 122880 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] can_verilog_source

Description: verilog code for can controller
Platform: | Size: 47104 | Author: subha | Hits:
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