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[WEB Code] clk

Description: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件
Platform: | Size: 1224 | Author: 王晨磊 | Hits:

[Other resource] clk

Description: c5000系列的clk程序，希望对大家有所帮助
Platform: | Size: 60303 | Author: wanglijia | Hits:

Description: VERILOG实现多时钟,可以应用于流水线.输入CLK,输出CLK1,CLK2,CLK3-Verilog realize multi-clock, can be applied to assembly line. Input CLK, the output CLK1, CLK2, CLK3
Platform: | Size: 1024 | Author: kaimen | Hits:

[Documents] clk

Description: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件-Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU
Platform: | Size: 1024 | Author: 王晨磊 | Hits:

[SCM] clk

Description: c5000系列的clk程序，希望对大家有所帮助-c5000 series clk procedures, and they hope to help everyone
Platform: | Size: 88064 | Author: wanglijia | Hits:

[VHDL-FPGA-Verilog] clk

Description: just division the clock into 2
Platform: | Size: 24576 | Author: zhuning | Hits:

[Com Port] 9600divider

Description: 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
Platform: | Size: 195584 | Author: liujieyu | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[VHDL-FPGA-Verilog] clk

Description: Verilog HDL clk 带延迟的时钟，对于处理时钟同步问题有益-Verilog HDL clk
Platform: | Size: 9216 | Author: 水 | Hits:

[SCM] msp430x54x-01-CLK

Description: MSP430 F5 系列时钟配置，网上的基本都是F1系列的-MSP430 F5 CLK setting
Platform: | Size: 11264 | Author: 陈武 | Hits:

[DSP program] clk

Description: DSK6455上的关于clk的程序，帮组你很好的学习DSp-clk for DSK6455
Platform: | Size: 136192 | Author: hushu | Hits:

[VHDL-FPGA-Verilog] clk

Description: 此程序句有多个clk去控制数据的传输，由于两个时钟不同，需要去经协调-iclk oclk
Platform: | Size: 912384 | Author: 陈利锋 | Hits:

[Other Embeded program] CLK

Description: ARM7系列中的LPC2132对CLK得设置以及一些小示例程序，都是开发板自带程序。-The LPC2132 ARM7 family CLK have set as well as some small sample programs are to develop board comes procedures.
Platform: | Size: 337920 | Author: 何鹏兵 | Hits:

[SCM] digital-clk

Description: 微机接口与原理的时钟实验带显示和输入-CLK 8086
Platform: | Size: 385024 | Author: hhj | Hits:

[VHDL-FPGA-Verilog] CLK

Description: QuartusII平台verilog语言实现的CLK下降沿测试-CLK falling edge QuartusII platform
Platform: | Size: 3072 | Author: FantasyDR | Hits:

[ELanguage] clk

Description: counting clk,, which count in increasing order..
Platform: | Size: 7168 | Author: Palwinder | Hits:

[Linux-Unix] clk

Description: general ColdFire CPU kernel clk handling
Platform: | Size: 1024 | Author: yongwingji | Hits:

[Other Embeded program] ADC0808-CLK-PULSE

Description: ADC0808与单片机的连接中，在延时函数中实现输出CLK脉冲，就可以既不用外接硬件，也不占用单片机本身的硬件资源，同样也达到了延时目的，可谓一举多得-ADC0808 with microcontroller connection, the delay function to achieve the output CLK pulse, you can either use an external hardware, nor hardware resources occupied by the microcontroller itself, also reached the purpose of delay, has multiple purposes
Platform: | Size: 76800 | Author: 陈贺 | Hits:

[Linux-Unix] clk-periph

Description: clk periph get parent for Linux v2.13.6.
Platform: | Size: 1024 | Author: berbinfu | Hits:

[Game Program] clk-periph

Description: clk periph get parent for Linux v2.13.6.
Platform: | Size: 1024 | Author: dsghhbnrjti | Hits:

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[WEB Code] clk

[Other resource] clk

[VHDL-FPGA-Verilog] clk_div

[Documents] clk

[SCM] clk

[VHDL-FPGA-Verilog] clk

[Com Port] 9600divider

[VHDL-FPGA-Verilog] clk_divider

[VHDL-FPGA-Verilog] clk

[SCM] msp430x54x-01-CLK

[DSP program] clk

[VHDL-FPGA-Verilog] clk

[Other Embeded program] CLK

[SCM] digital-clk

[VHDL-FPGA-Verilog] CLK

[ELanguage] clk

[Linux-Unix] clk

[Other Embeded program] ADC0808-CLK-PULSE

[Linux-Unix] clk-periph

[Game Program] clk-periph

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