Search - clock LCD VHDL

[Other resource] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642650 | Author: Jawen | Hits:

[Other resource] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3152400 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642816 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 时钟程序用于FPGA开发板上在LCD1602上显示时,分,秒,十分之一秒-Clock program for FPGA development board in the LCD1602 display hours, minutes, seconds, tenth of seconds
Platform: | Size: 2048 | Author: lijingfeng | Hits:

[VHDL-FPGA-Verilog] UP3_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified.
Platform: | Size: 728064 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] DS1307_LCD

Description: 通过IIC总线读写实时时钟DS1307，并把时、分、秒显示在12864液晶屏上，用的CycloneII EP2C8，Quartus环境-Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
Platform: | Size: 1311744 | Author: iversn | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 关于频率计程序的设计，LCD控制程序，PSK调制解调的控制程序，MSK调制解调控制程序，电梯控制程序，TLC5510控制程序，基带码发生器程序，电子琴程序，自动售货机程序，电子时钟程序，步进电机控制定位系统，波形发生器，出租车计价器，ADCO809-Procedures regarding the design of frequency meter, LCD control procedures, PSK modulation and demodulation of the control procedures, MSK modulation and demodulation control procedures, procedures for elevator control, TLC5510 control procedures, base-band code generator procedures, organ procedures vending machine procedures, electronic clock procedures, stepper motor control of positioning systems, waveform generator, Taximeter, ADCO809
Platform: | Size: 1277952 | Author: chenjy | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage signal detection/DEMO8 ADC voltage measurement/DEMO9 LCD driver circuit design
Platform: | Size: 736256 | Author: wang | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] lcd_driver

Description: 用FPGA控制12864液晶输出时钟信息很好可以根据自己的需要更改 -12864 LCD control with FPGA clock output information can be very good according to their need to change the
Platform: | Size: 406528 | Author: 刘军鹏 | Hits:

[VHDL-FPGA-Verilog] lcd_time

Description: 一个基于VHDL的多功能数字钟设计，能在LCD上显示时间，调整时间，整点报时，音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
Platform: | Size: 196608 | Author: 周殿凤 | Hits:

[VHDL-FPGA-Verilog] clock_vhdl

Description: 使用quartus ii开发的FPGA电子时钟的VHDL源代码，分模块写法，在1602液晶上显示，具有走时，调节时间功能-Using quartus ii the development of electronic clock FPGA VHDL source code, sub-module written in the 1602 LCD display, with travel time, settling time function
Platform: | Size: 617472 | Author: 陈飞 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 主要介绍VHDL下，电子时钟、LCD、LED、电子琴，电梯等开发程序。-Introduces the VHDL, the electronic clock, LCD, LED, keyboard, elevator and other development programs.
Platform: | Size: 13878272 | Author: huizeng | Hits:

[VHDL-FPGA-Verilog] LCD_CLOCK

Description: 用1602液晶显示的数字电子钟，并且可以用按键开关调整时间，日期，星期。-1602 LCD display with digital electronic clock, and the key switch can be used to adjust the time, date, week.
Platform: | Size: 3165184 | Author: 周航 | Hits:

[Windows Develop] fVerrilog_Devr

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Platform: | Size: 3170304 | Author: qtzx | Hits:

[VHDL-FPGA-Verilog] 1602lcdclock

Description: 使用vhdl语言在fpga平台上制作lcd电子钟，对于初学者，是一段很好的参考代码-Using VHDL language in fpga platform production LCD electronic clock, for beginners, is a very good reference code
Platform: | Size: 2048 | Author: 杜彬 | Hits:

[VHDL-FPGA-Verilog] uart_lcd

Description: 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company production run, prove that the program is stable and reliable. The clock is 50MHz, language VHDL, state machines.
Platform: | Size: 6435840 | Author: jiazhaorong | Hits:

[Other] VHDL

Description: FPGA开发板使用的一些实例，包括乐曲演奏器、1602液晶的多屏使用、液晶显示汉字、时钟。-Some examples of the use of FPGA development board, including the music player, the use of multi-screen LCD 1602, LCD characters, clock.
Platform: | Size: 4242432 | Author: li | Hits:

[DSP program] code

Description: vhdl code which includes various codes of clock divider uart lcd etc
Platform: | Size: 2028544 | Author: devi | Hits:

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