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[
VHDL-FPGA-Verilog
]
bdf
Description:
8位加法器的实现，仿真通过，并且包括仿真文件，在quartusii7.1下调试通过-8-bit adder realization, through simulation, and includes simulation document, under the debugger through quartusii7.1
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321536
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Author:
孙冰
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