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[VHDL-FPGA-Verilog] cntl_ddr3(xilinx)

Description: xilinx ddr3最新VHDL代码,通过调试-xilinx ddr3 latest VHDL code through debugging
Platform: | Size: 101376 | Author: zhang chi | Hits:

[VHDL-FPGA-Verilog] DDR3

Description: DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
Platform: | Size: 559104 | Author: andy | Hits:

[VHDL-FPGA-Verilog] 2048Mb_ddr3

Description: 美光DDR3存储器模型，用verilog语言编写，通用模型-DDR3 MEMORY
Platform: | Size: 41984 | Author: AricSnow | Hits:

[Other] DDR3-SDRAM-Verilog-Model(1)

Description: contains the information and codes of DDR3 memory model
Platform: | Size: 61440 | Author: vijju | Hits:

[VHDL-FPGA-Verilog] ddr3_mcb1

Description: 基于SPARTAN 6 的DDR3的实现。-The Verilog code for DDR3 on the SPARTAN 6
Platform: | Size: 9409536 | Author: steven | Hits:

[Software Engineering] DDR3-SDRAM-controller

Description: My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
Platform: | Size: 6144 | Author: thuanbk | Hits:

[source in ebook] DDR3-SDRAM-Verilog-Model

Description: ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
Platform: | Size: 61440 | Author: 陈国旗 | Hits:

[VHDL-FPGA-Verilog] DDR3-SDRAM-Verilog-Model

Description: 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。
Platform: | Size: 70656 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] DDR3 SDRAM Verilog Model

Description: ddr3的逻辑带么参考，有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
Platform: | Size: 70656 | Author: sss911 | Hits:

[VHDL-FPGA-Verilog] 11_ddr3_test

Description: fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
Platform: | Size: 7236608 | Author: 翻山越岭 | Hits:

[VHDL-FPGA-Verilog] ddr3_rw_ctrl

Description: verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
Platform: | Size: 1024 | Author: superali | Hits:

[VHDL-FPGA-Verilog] ddr3_test_top

Description: DDR3 test code 測試用的代碼 學習用,簡單的使用DDR3(DDR3 test code for learning verilog code study.)
Platform: | Size: 2048 | Author: JONESCHENG | Hits:

[VHDL-FPGA-Verilog] ddr3_128

Description: DDR3 读写操作，使用spartan6平台验证。(DDR3 read and write operations,the use of spartan6 platform validation.)
Platform: | Size: 10705920 | Author: 雷力风神 | Hits:

[Other] ddr3_test

Description: ddr3相关代码和基于ISE仿真调试，板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
Platform: | Size: 7467008 | Author: 田中泥 | Hits:

[VHDL-FPGA-Verilog] Verilog_1Gb_DDR3_G_Die

Description: ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
Platform: | Size: 33792 | Author: aikannba | Hits:

[VHDL-FPGA-Verilog] 35_OV7725_VGA_DDR3_LX16_joint

Description: 多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
Platform: | Size: 15978496 | Author: 黑色命运d幽默 | Hits:

[VHDL-FPGA-Verilog] DDR3_A4

Description: xilinx FPGA A7 驱动DDR3的DEMO例程(DEMO routines driven by Xilinx FPGA A7 for DDR3)
Platform: | Size: 24359936 | Author: amzhy8 | Hits:

[VHDL-FPGA-Verilog] DDR_sdram

Description: 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
Platform: | Size: 4935680 | Author: maxw123456789 | Hits:

[VHDL-FPGA-Verilog] 09_ddr3_test

Description: 利用vivado的MIG控制器来实现DDR3的读写(Using vivado's MIG controller to realize DDR3's read and write)
Platform: | Size: 24091648 | Author: 赵建奇 | Hits:

[assembly language] ddr3

Description: ALINX7010 ddr3读写测试仿真实验官方教程 附说明和代码 Vivado 实现(Alinx7010 DDR3 read write test simulation experiment official course Description and code attached Vivado implementation)
Platform: | Size: 3036160 | Author: 心素如简 | Hits:
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