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Description: easy pll,很好的PLL(锁相环设计工具)!
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Size: 108863 |
Author: 唐明 |
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Description: 锁相环设计文档和一个可执行文件-PLL design documents and an executable file
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Size: 108544 |
Author: KC_P |
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Description: 一篇简单易懂的关于数字锁相环概念原理设计的经典文章-An easy-to-read digital phase-locked loop on the concept of the classic principles of design article
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Size: 248832 |
Author: 林晓叶 |
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Description: easy pll,很好的PLL(锁相环设计工具)!-easy pll, good PLL (phase-locked loop design tools)!
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Size: 108544 |
Author: 唐明 |
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Description: 锁相环TB31202的c驱动程序，本人刚完成的项目采用的。运行正常！容易移植-TB31202 the c phase-locked loop driver, I have just completed the project adopted. Operating normally! Easy to transplant
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Size: 1024 |
Author: 莫潸 |
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Description: 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化，基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。因此，该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境；同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。-Introduce an approach based on frequency-locking phase-locked loop (FPLL) carrier tracking algorithm. Frequency tracking module can adapt to a larger dynamic range of the frequency change, software-based numerical control oscillator (NCO) module can achieve the very high frequency tracking accuracy. Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. Therefore, the FPLL carrier-based tracking algorithm can be adapted to signal the existence of a larger dynamic range and noise of the application environment at the same time, the PFD algorithm expression is simple, easy to use programmable digital devices.
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Size: 162816 |
Author: 何宁 |
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Description: PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code-PLL system LPF/PFD/VCO/Divider model in Matlab, the Matlab will PLL system model of each module, the easy analysis of the whole PLL loop stability characteristics, lock time ... ... the appendix contains a complete Matlab code
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Size: 92160 |
Author: xin |
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Description: 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of applications. With the traditional analog circuit implementation of the PLL in comparison, DPLL with high accuracy, free from the impact of temperature and voltage, loop bandwidth and center frequency adjustable programming, easy to build a high-order phase-locked loop, etc..
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Size: 1024 |
Author: hellen |
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Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
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Size: 466944 |
Author: xiang |
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Description: 给出了一种基于陷渡器的电磁轴承不平衡补偿的自适应方法。该方法不需要系统的具体
模型，通过实测的曼敏度函数求得丁矩阵．来保证系统稳定性。利用锁相环路实时跟踪转速．产
生与转速同频的正弦信号，在很大的转速范围内进行跟踪补偿。方法简单．易于实现，试验结果
表明了该方法的有效性-This paper presents a device based on the notch adaptive magnetic bearing unbalance compensation method. This method does not require a specific model of the system, through the measured D matrix Manmin fitness function obtained. To ensure system stability. The use of real-time tracking speed PLL. Generation and speed of the same frequency sinusoidal signal, a large speed within the tracking compensation. The method is simple. Easy to implement, test results show the effectiveness of the method
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Size: 2287616 |
Author: 黄航 |
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Description: 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using the FFT for fast FPGA computing, digital phase-locked loop to synchronize the measured signal to reduce the non-synchronous sampling error arising from implementation of the design and implementation are given. Digital PLL and FFT algorithm design and implementation using VHDL language, the program can improve the accuracy of harmonic analysis and response speed, and greatly streamline the hardware circuit, the system is very easy to upgrade.
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Size: 18432 |
Author: 何正亚 |
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Description: Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using PLL
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Size: 506880 |
Author: 林端 |
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Description: easy pll，非常好的的PLL(锁相环设计工具)!
-easy pll very good PLL (phase-locked loop design tools)
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Size: 93184 |
Author: 奉献 |
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Description: 第三批捕获单元的捕获程序，简单易懂，适用于各中文件，做学习用-dsp spwm cap easy learn
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Size: 1024 |
Author: 陈芳 |
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Description: 本内容详细介绍了PLL锁相环技术的具体的工作原理，字迹简单易懂，很容易能明白锁相环的工作过程，值得参阅-The detailed description of the specific works PLL phase-locked loop technology, writing easy to understand, it is easy to understand the work process can be phase-locked loop, it is worth see
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Size: 36864 |
Author: dan |
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Description: A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is fed back toward the input forming a loop.-A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is fed back toward the input forming a loop.
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Size: 11264 |
Author: mojtaba |
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Description: Hittite公司以创新的设计使得其PLL产品性能优异，在相位噪声，杂散方面有着卓越表现，其芯片的高集成度使得外围电路简单，设计方便。所以随着电子技术的发展，对频率源的相位噪声性能要求越来越高，Hittite的低相位噪声PLL，在物理、天文、无线电通信、雷达、航空、航天以及精密计量、仪器、仪表等各种领域里都将大有用武之地。-The Hittite companies with innovative design makes the PLL excellent product performance, the phase noise, spurious aspects with excellence, its high integration chip makes the peripheral circuit is simple and easy design. So with the development of electronic technology, phase noise performance of frequency source is more and more high, the Hittite low phase noise PLL, in physics, astronomy, radio communication, radar, aviation, aerospace and precision measurement, instruments, meters and other fields will be great.
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Size: 4281344 |
Author: 915809706 |
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Description: pll锁相环simulink模型，通俗易懂，可以实现的模型(Pll phase locked loop simulink model, easy to understand, can achieve the model)
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Size: 470016 |
Author: 182505196527
|
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Description: easy pll,很好的PLL(锁相环设计工具)!()
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Size: 92160 |
Author: losyream |
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Description: easy pll,很好的PLL(锁相环设计工具)!()
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Size: 92160 |
Author: AR%400235 |
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