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[VHDL-FPGA-Verilog] cf_interleaver2 DL : 0: interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials are intertwined
Update : 2025-02-17 Size : 352kb Publisher : 陈朋
[Streaming Mpeg4] bit_intealeaver1 DL : 0: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Update : 2025-02-17 Size : 1kb Publisher : wenjuner
[Embeded-SCM Develop] turbo-interleaver DL : 0: 基于FPGA的Turbo码交织器的设计与实现比较实用-FPGA-Based Turbo Code Interleaver Design and Implementation of a more practical
Update : 2025-02-17 Size : 363kb Publisher : mediative
[matlab] rs_cnv DL : 0: 由RS码、卷积码构成的级联码，结合交织技术，用于信道编码-RS code and convolution code, combine with interleaving, use for channel coding.
Update : 2025-02-17 Size : 4kb Publisher : 娜
[Program doc] qpp_interleaver_document DL : 0: documents for qpp interleaver for turbo coding
Update : 2025-02-17 Size : 603kb Publisher : ren