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[GUI Develop] VHDLshixuluoji

Description: 简单的12位寄存器 带三态输出的8位D寄存器：74374 简单的锁存器-simple register with 12 three-state output of eight D Register : 74374 simple latch
Platform: | Size: 1024 | Author: 赵天 | Hits:

[VHDL-FPGA-Verilog] codeofvhdl2006

Description: 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Platform: | Size: 44032 | Author: senkong | Hits:

[SCM] digital_cymometer

Description: 简易数字频率计利用复杂可编程逻辑器件FPGA,VHDL编程将所有功能模块集成在一块芯片上。功能模块包括时基脉冲发生器、计数器、数据锁存器和显示电路4部分。设计时先分别设计各功能模块，并调试得到正确仿真结果，然后将各个功能模块组合起来。最后作整体仿真、下载，得到实物。由于采用纯数字硬件设计制作，稳定性、可靠性远远高于使用单片机或模拟方式实现的系统，外围电路简单。该数字频率计达到预期要求，实现了可变量程测量，测量范围0.1Hz—9999MHz，精度可达0.1Hz。-Simple digital frequency meter using complex programmable logic device FPGA, VHDL programming integration of all functional modules on a single chip. Functional modules, including time-base pulse generator, counters, and display data latch circuit 4. Design before the design of various functional modules, respectively, and debugging simulation results correctly, and then combine the various functional modules. Finally, for the overall simulation, download, be kind. As a result of the production of digital hardware design, stability, reliability is far higher than the use of single-chip microcomputer or analog means of the system, a simple peripheral circuits. The digital frequency meter to achieve the desired requirements of the variable-range measurement, measuring range 0.1Hz-9999MHz, accuracy up to 0.1Hz.
Platform: | Size: 412672 | Author: 严术骞 | Hits:

[SCM] testctl

Description: 本程序实现了一个数字频率计。它由一个测频控制信号发生器TESTCTL，8个有时钟的十进制计数器CNT10，一个32位锁存器REG32B组成。-This procedure implements a digital frequency meter. It consists of a frequency control signal generator TESTCTL, 8 which have the metric system clock counter CNT10, a 32-bit latch REG32B component.
Platform: | Size: 1024 | Author: liushenshen | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块. -Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
Platform: | Size: 13312 | Author: 侯治强 | Hits:

[VHDL-FPGA-Verilog] pinluji

Description: 四位十进制频率计设计 包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Platform: | Size: 11264 | Author: 深空 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] SR_Latch

Description: RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.-RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
Platform: | Size: 354304 | Author: Seungyun | Hits:

[Embeded-SCM Develop] CPLD

Description: 风力发电设备用CPLD外围控制程序。包括故障锁存，IO口输出输入，地址线译码等。-Wind power generation equipment control procedures external CPLD. Including the fault latch, IO I O, address decoding and other lines.
Platform: | Size: 73728 | Author: 吕佃顺 | Hits:

[SCM] qiangdaqi

Description: 　 (1) 抢答器线路测试功能 　　为了保证比赛的正常进行，比赛前需要调试线路能否正常工作。 　　 (2) 第一抢答信号的鉴别和锁存功能 　　可以判断谁最先抢到回答的资格，其相应的绿灯表示抢答成功，并具有锁存功能，一直到下一题开始。 　　 (3) 犯规警示功能 　　可以判断出参赛者有没有在主持人读题的期间按下抢答器，有则相应的红灯亮，同时取消其本轮抢答资格。 　　 (4) 计时功能 　　可以预置时间，可以进行倒计时并且将时间显示出来。 　　 (5) 计分功能 可以实现加分，并且显示出来 -(1) Answer line testing device in order to ensure the normal game, the need to debug line before the game can work properly. (2) Answer the first to identify and latch signals to determine who can be the first to get the qualifications to answer, and its corresponding Answer green that success and with latch function, until the beginning of the next title. (3) foul warning function can be judged contestants have read in the host during the press Answer questions, and there is a corresponding red light, at the same time cancel the current round of qualifications Answer. (4) The time functions can be preset time, the countdown can be displayed and the time. (5) scoring function points can be achieved and displayed.
Platform: | Size: 956416 | Author: 孙国栋 | Hits:

[SCM] suocunqivhdl

Description: 这是关于锁存器的vhdl语言。。大家相互交流-This is the latch on the vhdl language. . We each other. .
Platform: | Size: 3072 | Author: 于振雨 | Hits:

[Other] vhdl

Description: 实现代码，A、B为输入、Y为输出，它们为8位向量。OE为输出使能，低电平有效。IE为输入锁存时能，上升沿有效。Ci为进位输入，Co为进位输出。 S0、S1、S2为运算逻辑选择输入： ，用vhdl语言编写，基于数字电路。-Implementation code, A, B input, Y the output, they are 8-bit vector. OE to output enable, active low. IE when the input latch, rising edge and effective. Ci for the Carry input, Co to carry out. S0, S1, S2 for the arithmetic logic selection input: using vhdl language, based on digital circuits.
Platform: | Size: 1024 | Author: youruo | Hits:

[DSP program] bit4latchtest

Description: 4 bit latch for verilog prrpose helpful in verification
Platform: | Size: 138240 | Author: rahul | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计 一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计 二．实验内容 设计基于ROM的正弦波发生器，对其编译，仿真。 具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC-VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..
Platform: | Size: 311296 | Author: yuxiang | Hits:

[VHDL-FPGA-Verilog] 4-10-VHDL-f1

Description: 四位10进制VHDL频率计设计说明 四位频率计的结构包括一个测频率控制信号发生器、四个十进制计数器和一个十六位锁存器（本例中所测频率超过测频范围时有警示灯）。-Four 10-digit frequency counter VHDL design description of the structure of the four frequency meter includes a measuring frequency control signal generator, four decimal counter and a sixteen bit latch (in this case the measured frequency over a frequency measurement range warning lights).
Platform: | Size: 54272 | Author: 韦昊斯 | Hits:

[Software Engineering] vhdl

Description: 3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
Platform: | Size: 483328 | Author: 绿茶混咖啡 | Hits:

[VHDL-FPGA-Verilog] VHDL-language

Description: 用VHDL语言完成4位锁存器、测频控制器的设计-VHDL language to complete 4-bit latch, the measured frequency controller design
Platform: | Size: 1024 | Author: denwei0011 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 电路主要由七个模块组成：时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟；二分频模块用于对1Hz的时钟信号二分频；测量/校验选择模块用于功能选择；计数模块用于对输入的cp信号计数；送存选择、报警电路根据选择的量程送存信号并显示单位，在超出所选量程时报警；锁存器锁存要显示的结果；扫描显示模块在1KHz的扫描时钟下，依次扫描三个数码管，并显示结果。-The circuit consists of seven main modules: clock generation module is used to generate 1KHz scan clock and 1Hz clock frequency module for 1Hz clock signal frequency measurement/calibration selection module for function selection count module for the input the cp signal count deposit options, alarm deposit signal circuit according to the selected range and display units, within the selected range alarm latch latches to be displayed scanning display module at 1KHz the scan clock, scan the three digits, and displays the results.
Platform: | Size: 2048 | Author: 张骞 | Hits:

[Other] VHDL

Description: 具有锁存功能，报警功能，可判断第一抢答者并报警指示抢答成功，其他组抢答均无效。-Latch function, alarm function, can be judged First Responder and alarm indication answer other answer is invalid.
Platform: | Size: 8192 | Author: 林敏 | Hits:
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