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Description: 这是libero8.0软件的安装方法，及该软件的 license.ACTEL的FPGA的资料及软件的使用都非常少，故先传这个license-This is libero8.0 software installation methods, and the software license.ACTEL the FPGA information and software are very small, so the first mass of the license
Platform: | Size: 20480 | Author: 张全文 | Hits:

[VHDL-FPGA-Verilog] Libero8.0

Description: Libero8.0_教程,希望学习fpga的同学能够得到点帮助。-Libero8.0_ tutorial, I hope to learn the FPGA can be to help the students.
Platform: | Size: 3816448 | Author: 江鹏 | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] Libero8.5_UG

Description: Libero集成设计环境(IDE)8.5版本，这套完整的软件设计工具系列已进一步扩展，支持新近推出的nano版本IGLOO和ProASIC3现场可编程门阵列(FPGA)。-Libero Integrated Design Environment (IDE) 8.5 version, this complete series of software design tools have been further expanded to support the recently introduced nano versions of IGLOO and ProASIC3 field-programmable gate array (FPGA).
Platform: | Size: 2481152 | Author: 陈俊江 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用VHDL语言编程实现UART，8位数据位，校验位自己可以加！LIBERO仿真正确！-VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly!
Platform: | Size: 14336 | Author: funny | Hits:

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[Other] License

[VHDL-FPGA-Verilog] Libero8.0

[VHDL-FPGA-Verilog] uart8

[VHDL-FPGA-Verilog] Libero8.5_UG

[VHDL-FPGA-Verilog] UART

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