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[Other] License

Description: 这是libero8.0软件的安装方法，及该软件的 license.ACTEL的FPGA的资料及软件的使用都非常少，故先传这个license
Platform: | Size: 20330 | Author: 张全文 | Hits:

[Other resource] Libero8.0

Description: Libero8.0_教程,希望学习fpga的同学能够得到点帮助。
Platform: | Size: 3816770 | Author: 江鹏 | Hits:

[SourceCode] 带仿真的双端口RAM工程 例程都是“IP核+简单逻辑控制 ”来解答各位ACTEL初学者的疑惑 。以上代码都是验证通过，开发环境LIBERO8.

Description: 带仿真的双端口RAM工程 例程都是“IP核+简单逻辑控制 ”来解答各位ACTEL初学者的疑惑 。以上代码都是验证通过，开发环境LIBERO8.0
Platform: | Size: 655017 | Author: 1260086278 | Hits:

[Other] License

Description: 这是libero8.0软件的安装方法，及该软件的 license.ACTEL的FPGA的资料及软件的使用都非常少，故先传这个license-This is libero8.0 software installation methods, and the software license.ACTEL the FPGA information and software are very small, so the first mass of the license
Platform: | Size: 20480 | Author: 张全文 | Hits:

[VHDL-FPGA-Verilog] Libero8.0

Description: Libero8.0_教程,希望学习fpga的同学能够得到点帮助。-Libero8.0_ tutorial, I hope to learn the FPGA can be to help the students.
Platform: | Size: 3816448 | Author: 江鹏 | Hits:

[VHDL-FPGA-Verilog] CRACK

Description: 附件为Synplify9.2.2的license和破解方法-Annex for the license and crack Synplify9.2.2 method
Platform: | Size: 16384 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] Libero8.5_UG

Description: Libero集成设计环境(IDE)8.5版本，这套完整的软件设计工具系列已进一步扩展，支持新近推出的nano版本IGLOO和ProASIC3现场可编程门阵列(FPGA)。-Libero Integrated Design Environment (IDE) 8.5 version, this complete series of software design tools have been further expanded to support the recently introduced nano versions of IGLOO and ProASIC3 field-programmable gate array (FPGA).
Platform: | Size: 2481152 | Author: 陈俊江 | Hits:

[SCM] DDS

Description: 开发环境为Libero8.3,以DDS为基础设计了移频轨道信号发码器-Use Libero8.3 as the developing environment, designed a track signal frequency shift codec based on DDS
Platform: | Size: 4015104 | Author: Vicky Yang | Hits:

[VHDL-FPGA-Verilog] Libero8.3

Description: 介绍了 Actel FPGA 的集成开发环境 IDE 的使用，从软件的安装和设置，以及 通过一个简单的例子说明如何使用 IDE中集成的第三方软件，如：Synplify、ModelSim等，可以帮助读者快速入门，缩短开发时间。-Actel FPGA introduced the use of IDE integrated development environment, from software installation and setup, as well as through a simple example of how to use the IDE, integrated third-party software, such as: Synplify, ModelSim, etc., can help readers get started quickly, shortening development time.
Platform: | Size: 2623488 | Author: anranxjk | Hits:

[VHDL-FPGA-Verilog] 4X

Description: VHDL实现的4位乘法器，绝对好用，libero8.5仿真没问题！-VHDL implementation of the 4-bit multiplier
Platform: | Size: 1024 | Author: funny | Hits:

[VHDL-FPGA-Verilog] how_to_use_Libero8

Description: 是libero的使用说明，如果想使用actelfpga的libero软件可以试试它。-the reference of actel fpga soft Libero8.5, and it s good tool for new learner.
Platform: | Size: 2618368 | Author: 书荣 | Hits:

[MPI] z8051

Description: 在libero8.1环境下，用Verilog描述的8051内核，可以包括各个基本模块，可以仿真。-In the libero8.1 environment described in Verilog 8051 core, including the basic module can be simulated.
Platform: | Size: 4291584 | Author: 章泽良 | Hits:

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