Description: 可以自由开发的MIPS仿真器模型(.exe),指令执行动画显示.通过修改graphics和对应的元件和互联文件(.dit)可以自己画流水线,其中.dit文件使用简单的硬件描述语言编写.而mipsit是对应的软件开发环境,为自己设计的流水线编程.学习体系结构的好东西-This is a system consisting of a
software development environment and a highly flexible microarchitecture simulator
used for pipeline studies. Platform: |
Size: 3203072 |
Author:zx |
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Description: x86体系结构的资料很少见，因为是专利技术，本资料是研究机构多年研究思考的结果，不见得就是对x86的准确描述，但对于x86体系结构的理解有很大帮助。对微处理器学习和设计者来说亦非常有价值
-x86 architecture, the data is rare, because it is patented technology, research institutions, this information is to think the results of years of research, is not necessarily an accurate description of the x86, but x86 architecture, the understanding of much help. Learning and designer of the microprocessor is also very valuable to Platform: |
Size: 626688 |
Author:Zack |
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Description: Core 2 Duo处理器的参考内容与基于英特尔微处理器架构。-References to the Core 2 Duo processor refer to processors based on the Intel®
Core™ microarchitecture. Platform: |
Size: 2642944 |
Author:大林 |
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Description: Intel_AMD_处理器结构介绍资料。源于哥本哈根大学的一份研究报告，内容比较详细，包括了很多相关文档的互联网连接-Intel_AMD_processor_architecture_description_material. this is from a research report of Copenhagen University Platform: |
Size: 825344 |
Author:wgx |
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Description: 性能优化，优化编译器，优化内存使用，优化语言结构等-This series of five manuals describes everything you need to know about optimizing code for x86 and x86-64 family microprocessors, including optimization advices for C++ and assembly language, details about the microarchitecture and instruction timings of Intel, AMD and VIA processors, and details about different compilers and calling conventions. Platform: |
Size: 4151296 |
Author:bugudo |
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Description: The MASE code is stable, documentation is included in the test distribution, the code is awaiting integration into the main SimpleScalar 4.0 code base. A report on the MASE microarchitecture simulation infrastructure is available here. Details on the latest version of MASE and updates are contained in the release documentation.
-The MASE code is stable, documentation is included in the test distribution, the code is awaiting integration into the main SimpleScalar 4.0 code base. A report on the MASE microarchitecture simulation infrastructure is available here. Details on the latest version of MASE and updates are contained in the release documentation.
Platform: |
Size: 3643392 |
Author:Jack |
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Description: This document describes the use of the BookSim interconnection network simulator. The simulator
is designed as a companion to the textbook \Principles and Practices of Interconnection Networks"
(PPIN) published by Morgan Kaufmann (ISBN: 0122007514) and it is assumed that is reader is
familiar with the material covered in that text.
This user guide is fairly brief as, with most simulators, the best way to learn and understand
the simulator is to study the code. Most of the simulator s components are designed to be modular
so tasks such as adding a new routing algorithm, topology, or router microarchitecture should not
require a complete redesign of the code. Platform: |
Size: 596992 |
Author:patiar |
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Description: SOC微体系结构课件，学习CPU的组成，系统原理-SOC microarchitecture courseware, learning the composition of CPU, system theory Platform: |
Size: 11195392 |
Author:顾喜玺 |
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Description: The microarchitecture of Intel, AMD and VIA CPUs (3/5).
An optimization guide for assembly programmers and compiler makers.
By Agner Fog. Technical University of Denmark. Platform: |
Size: 1584128 |
Author:regx |
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Description: 介绍怎样去设计一种专用DSP
1. DSP fundamental,processor architectures, real-time system and design of embedded systems
2. Numberical representation and precision control of fixed-point number
3. ASIP and DSP architectures for different requirements and applications.
4. Intro to design methodologies for ASIP and DSP firmware
5. a DSP processor with an intuitive assembly instruction set
6. Profiling for ASIP IS design
7. IS design technique
8. Intro to toolchain
9. Benchmarking of assembly IS
10. Microarchitecture design
11. RF design
12. ALU
13. MAC
14. Control path
15. Design and implementation of memory subsys and address generators
16. DSP peripherals
17. funcational acceleration and DSP accelerators
18. Firmware design
19. Integration and verification of ASIP
20. parallel ASIP for streaming signal processing(embedded dsp processor design) Platform: |
Size: 17182720 |
Author:nickwang1982 |
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Search - microarchitecture