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[Other resource] miniuart_vhdl

Description: 用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
Platform: | Size: 4182 | Author: djksdf | Hits:

[Other] rs232

Description: this is a vhdl version of MiniUART implementation
Platform: | Size: 964309 | Author: kevin | Hits:

[Communication-Mobile] miniuart

Description: vhdl实现miniUART代码 分模块设计和状态机设计,内核超级小
Platform: | Size: 89978 | Author: harrybird | Hits:

[Other resource] miniuart.tar

Description: miniuart 串口源码程序 VHDL语言
Platform: | Size: 5712 | Author: yongqin2005 | Hits:

[Other resource] miniuart

Description: This is a uart source written by VHDL .widely used and compatible with Whibone.
Platform: | Size: 9299 | Author: FLY | Hits:

[VHDL-FPGA-Verilog] miniuart_vhdl

Description:
Platform: | Size: 4096 | Author: djksdf | Hits:

[Other] rs232

Description: this is a vhdl version of MiniUART implementation
Platform: | Size: 964608 | Author: kevin | Hits:

[Communication-Mobile] miniuart

Description: vhdl实现miniUART代码 分模块设计和状态机设计,内核超级小-VHDL code miniUART to achieve sub-module design and state machine design, super small kernel
Platform: | Size: 90112 | Author: harrybird | Hits:

[VHDL-FPGA-Verilog] miniuart.tar

Description: miniuart 串口源码程序 VHDL语言-miniuart serial VHDL language source program
Platform: | Size: 6144 | Author: yongqin2005 | Hits:

[VHDL-FPGA-Verilog] miniuart

Description: This is a uart source written by VHDL .widely used and compatible with Whibone.-err
Platform: | Size: 9216 | Author: FLY | Hits:

[VHDL-FPGA-Verilog] miniUART

Description: 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
Platform: | Size: 9216 | Author: 甘甜 | Hits:

[VHDL-FPGA-Verilog] miniUart

Description: 一个简单的uart的VHDL描述，希望对大家有点帮助-A simple UART in VHDL description, I hope all of you a little help
Platform: | Size: 19456 | Author: 肖冠兰 | Hits:

[VHDL-FPGA-Verilog] miniuart.tar

Description: Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
Platform: | Size: 6144 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] miniuart.tar

Description: 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL description with a simple UART interface
Platform: | Size: 6144 | Author: elvis | Hits:

[VHDL-FPGA-Verilog] system05_latest.tar

Description: 6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz
Platform: | Size: 29696 | Author: amin | Hits:

[VHDL-FPGA-Verilog] miniuart-1.0.0.tar

Description: wishbone uart controller
Platform: | Size: 104448 | Author: tekker | Hits:

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