Search - msb verilog

[Other Embeded program] msblsb_seperation

Description: This program seperates MSB and LSB of a two digit number in verilog and implemented on SPARTAN 3E.
Platform: | Size: 284672 | Author: kal | Hits:

[VHDL-FPGA-Verilog] alu32bit

Description: verilog hdl alu module it is 32bit alu and 1bit alu
Platform: | Size: 368640 | Author: park | Hits:

[VHDL-FPGA-Verilog] MSB_search_verilog

Description: 使用Verilog实现16位数据最高有效位的查找-use verilog to search msb of 16 bits data
Platform: | Size: 131072 | Author: fc | Hits:

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and modified paper output can be provided. Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
Platform: | Size: 783360 | Author: anandg | Hits:

[VHDL-FPGA-Verilog] Lab_02

Description: Verilog 3-to-8 Decoder on Spartan3E. Use 3 switches (SW[2:0]) as inputs. Keep SW[2] as MSB. Use 8 LEDs (LD[7:0]) as decoded outputs. i.e. if all input switches are turned off, LD0 should light up.
Platform: | Size: 91136 | Author: kacian | Hits:

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[Other Embeded program] msblsb_seperation

[VHDL-FPGA-Verilog] alu32bit

[VHDL-FPGA-Verilog] MSB_search_verilog

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

[VHDL-FPGA-Verilog] Lab_02

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