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[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[VHDL-FPGA-Verilog] Lab20

Description: the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.
Platform: | Size: 56320 | Author: 王琪 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
Platform: | Size: 2048 | Author: 王森 | Hits:

[Other] SignalTapII

Description: Altera公司Quartus II软件的逻辑分析使用流程，中文版本。该文件详细说明了使用SingalTapII的流程和基本使用方法，对使用FPGA的人有很大帮助。
Platform: | Size: 1125376 | Author: 邓奕堃 | Hits:

[Embeded-SCM Develop] Ddelay

Description: 在Quartus下使用D触发器来加入延迟，每个D触发器增加半个周期的延迟，稍加更改可以得到不同的延迟。-In Quartus using D flip-flop to join the delay, each D flip-flop raised a half-cycle delay, a little change can be a different delay.
Platform: | Size: 377856 | Author: 桃子 | Hits:

[VHDL-FPGA-Verilog] FSM_Moore

Description: altera Quartus II FSM使用 可設定時間波形，手動調整波形頻率。 (含電路) -altera Quartus II FSM can be set using the time waveform, manually adjust the frequency waveform. (With circuit)
Platform: | Size: 114688 | Author: 陳小龍 | Hits:

[VHDL-FPGA-Verilog] TLC5510

Description: altera Quartus II TLC晶片控制 可控制暫存器，手動調整內碼。 (含電路) -altera Quartus II TLC chip control registers can be controlled manually adjust the code. (With circuit)
Platform: | Size: 129024 | Author: 陳小龍 | Hits:

[SCM] dmc_verilog

Description: 本示例中使用了一个DCM模块，将输入时钟50MHz，倍频到100MHz，分频到25MHz，不同的频率值通过LED进行演示。-This example uses a DCM module, the input clock 50MHz, frequency-doubled to 100MHz, frequency to 25MHz, the frequency of different values demonstrated through the LED.
Platform: | Size: 631808 | Author: 沈天平 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] qts_qii53008

Description: Quartus II SignalProbe说明文档，详细说明了如何在QuartusII中使用SignalProbe进行快速调试。-Quartus II SignalProbe documentation detailing how to use QuartusII rapid SignalProbe debugging.
Platform: | Size: 572416 | Author: 杨开轶 | Hits:

[Com Port] openrisc_hello-uart

Description: OpenRisc精简版本，uart输出，soc的好材料-OpenRisc streamlined version, uart output, soc good material
Platform: | Size: 789504 | Author: 万于 | Hits:

[Embeded-SCM Develop] quartus

Description:
Platform: | Size: 10531840 | Author: liuhongjie | Hits:

[matlab] matlab_quartus

Description: 可以方便地将matlab里的数据导入quartus中的波形仿真文件中，很有用-Matlab can easily import the data in waveform simulation Quartus document, very useful
Platform: | Size: 1024 | Author: 侯训平 | Hits:

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] ug_lpm_rom

Description: quartus rom的生成 运用matlab生成.mif或.hex文件 载入rom表-quartus rom the use of matlab generated generation. mif or. hex file loading rom Table
Platform: | Size: 824320 | Author: 王欣欣 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[Multimedia Develop] 55555555

Description: quartur2是十分有用的，这是课件，里面有具体的操作，希望对大家有用，谢谢。-quartur2 is very useful, which is courseware, there are specific operations, in the hope that useful, thank you.
Platform: | Size: 844800 | Author: quanlina | Hits:

[Com Port] QUART

Description: 通信串口事例 ARM7 速率自适应-ARM7 QUART
Platform: | Size: 2048 | Author: niao0311 | Hits:
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