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Search - rs flip flop

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[matlab] RSchufaqi

Description: 用matlab中的simulink模拟的一个rs触发器 -Simulink with matlab simulation in a rs flip-flop
Platform: | Size: 5120 | Author: liqin | Hits:

[VHDL-FPGA-Verilog] djkrs

Description: d,jk,rs触发器的vhdl语言实现，简单明了-d, jk, rs flip-flop of the VHDL language, simple and clear
Platform: | Size: 70656 | Author: 周军 | Hits:

[VHDL-FPGA-Verilog] mimasuo

Description: vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验-Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
Platform: | Size: 97280 | Author: wan | Hits:

[VHDL-FPGA-Verilog] rs_1

Description: rs触发器的设计，是用vhdl实现的，欢迎下载。-rs flip-flop design is achieved using vhdl.
Platform: | Size: 21504 | Author: Mr zhang | Hits:

[Other] jk

Description: jk触发器在rs触发器的基础上进行改进，可以将jk=1的输入状态定义为合法状态。-jk flip-flop in the rs flip-flop based on the improvement can be jk = 1 of the input state is defined as the legal state.
Platform: | Size: 28672 | Author: 李本 | Hits:

[VHDL-FPGA-Verilog] bch

Description: Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
Platform: | Size: 15360 | Author: santhu | Hits:

[2D Graphic] LabVIEW

Description: 四选一数据选择器.vi 3-8译码器.vi 全减器.vi 时钟.vi RS触发器.vi-4 Select a data selector. Vi 3-8 decoder. Vi Full reduction device. Vi Clock. Vi RS flip-flop. Vi
Platform: | Size: 72704 | Author: 宋佩 | Hits:

[VHDL-FPGA-Verilog] jishuji

Description: 将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成一个FPGA芯片中模拟其功能，并研究其相互转化的方法。-The basic RS flip-flop, synchronous RS flip-flop, integrated JK flip-flop, D flip-flop while a FPGA chip analog integrated function, and to study their mutual transformation method.
Platform: | Size: 1303552 | Author: shenlina | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 多路抢答器 VHDL语言设计 抢答器是各类竞赛常用的仪器设备之一，它能快速、准确地判决并显示出第一抢答者。本文作者采用MAXPLUSII 软件和MAX7000S芯片，提出了一种四路抢答器的设计方案。该方案具有判断准确、硬件电路简单、容易实现等优点。 关键字：抢答器 竞争 RS触发器 EDA -Multiple Responder Responder VHDL language design competition of various kinds of equipment used, it can quickly and accurately answer in the first sentence and show those. The author uses MAXPLUSII MAX7000S chip software and proposes a four-way Responder design. The program has to determine accurately, the hardware circuit is simple, easy to implement and so on. Keywords: Responder competitive EDA RS flip-flop
Platform: | Size: 80896 | Author: 王天宇 | Hits:

[VHDL-FPGA-Verilog] Trigger

Description: 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
Platform: | Size: 925696 | Author: baoguocheng | Hits:

[VHDL-FPGA-Verilog] asynchronous-sequential-circuits

Description: 利用基本RS触发器设计电平异步时序电路的方法 此文档帮助读者设计数字逻辑电路，并非VHDL语言实现-The use of the basic RS flip-flop design level asynchronous sequential circuits This document is to help readers design digital logic circuits, not the VHDL language
Platform: | Size: 798720 | Author: 东方不败 | Hits:

[SCM] timer555

Description: 本文以555定时器为核心，辅以基本RS触发器，设计了一套可以使用按键开关的双音报警电路，能够输出高、低音阶交替的报警音，并设有常亮和闪烁两种LED报警灯。该电路既可以作为独立的报警器，也可以稍作改动，作为一个复杂系统中的报警模块使用。采用multisim绘制-555 timer as the core, supplemented by basic RS flip-flop design can be set using the key switch, dual-tone alarm circuit can output high, low scale alternating alarm tone, and has two LED lit and flashing alarm lamp. The circuit either as a standalone alarm can also make a little change, as the alarm module in a complex system. Multisim draw
Platform: | Size: 415744 | Author: Youyou | Hits:

[Software Engineering] VHDL_trigger

Description: 本实验是VHDL的触发器实现，将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成在一个CPLD芯片中模拟其功能，并研究其相互转化的方法。-This experiment is the trigger of VHDL realize, will be basically RS flip-flop, synchronous RS flip-flop, the integrated JK flip-flop, D flip-flops simultaneously integrated in a CPLD chip to simulate its functionality, and to study their mutual transformation approach.
Platform: | Size: 728064 | Author: 陈芳 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
Platform: | Size: 1024 | Author: 黄华 | Hits:

[VHDL-FPGA-Verilog] rschufaqi

Description: 此程序是根据rs触发器的功能用VHDL语言描述的RS触发器，供同学们学习交流-This program is based on the RS flip-flop rs flip-flop functions described in VHDL language for students learning exchanges
Platform: | Size: 111616 | Author: 魏银玲 | Hits:

[FlashMX] 20140610swf4

Description: 电子技术swf 动画 27.基本RS触发器 28.环形多谐振荡器 29.自激振荡的工作原理 30.施密特触发器 31.脉冲的概念 32.寄存器 33.位移寄存器-Electronic technology swf animation 27 basic RS flip-flop 28. The ring multivibrator 29. The working principle of self-excited oscillation 30. Schmitt trigger The concept of pulse 31 32. Register 33. Shift registe
Platform: | Size: 5846016 | Author: | Hits:

[SCM] external-interruption

Description: 1、电路：引用“并口接口输入输出”，增加RS触发器电路，其输出控制T0（P3.4）外部计数输入端。 程序：计1个外部脉冲，LED数码显示段加1。 2、电路：引用“2.并口接口输入输出”，增加RS触发器电路，其输出控制外部中断-INT1（P3.3）。 程序：对每次中断，在左边第一个LED数码显示器上进行计数。-1, the circuit: Reference Parallel Interface input and output, adds RS flip-flop circuit, the output control T0 (P3.4) external count input.   Program: an external pulse meter, LED digital display segment plus one. 2, circuit: Reference 2. Parallel Interface input and output, adds RS flip-flop circuit, the output controls the external interrupt-INT1 (P3.3).         Program: for each interrupt on the left of the first LED digital display counts.
Platform: | Size: 2048 | Author: 诗意 | Hits:

[GPS develop] rs-code

Description: VHDL Code for D-Flip Flop & Matching Unit
Platform: | Size: 16384 | Author: Mohammed Ismail | Hits:

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