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[VHDL-FPGA-Verilogcadence-datasheet

Description: SynTest-Cadence : One-Pass DFT and Synthesis Solution for ASICs
Platform: | Size: 154624 | Author: firas | Hits:

[JSP/Javasyntest

Description: 本程序主要应用于毕业设计,实现成绩查询,录入等功能,系统是MVC架构,方便维护和管理-Graduated from the design, implementation, performance queries, entry and other functions
Platform: | Size: 1323008 | Author: 赵晨 | Hits:

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