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[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9682 | Author: 李志 | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1325 | Author: 陈刚峰 | Hits:

[Other resource] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761622 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9216 | Author: 李志 | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1024 | Author: 陈刚峰 | Hits:

[VHDL-FPGA-Verilog] FIFO_Buffer(verilog)

Description: 这是一个FIFO_Buffer的verilog代码.-This is a FIFO_Buffer the Verilog code.
Platform: | Size: 71680 | Author: 郑海伟 | Hits:

[Software Engineering] 24c512

Description: AT24C512是ATMEL公司新近推出的具有I2C总线容量达512Kbit（64K×8）的E2PROM，该芯片的主要特性如下：存储容量为65536byte；与100kHz、400kHz、1MHzI2C总线兼容；100000次编程/擦写周期；单电源、读写电压为1.8V～5.5V；ESD保护电压>4kV；数据可保存40年；写保护功能，当WP为高电平时，进入写保护状态；CMOS低功耗技术，最大写入电流为3mA；128byte页写入缓存器；自动定时的写周期；具有8引脚DIP及20引脚SOIC封装等多种封装形式。-ATMEL Corporation AT24C512 is a newly launched I2C bus has a capacity of 512Kbit (64K × 8) of the E2PROM, the chip s main characteristics are as follows: storage capacity for 65536byte with 100kHz, 400kHz, 1MHzI2C Bus compatible 100000 times Programming/rub write cycle single-supply, read and write voltage of 1.8V ~ 5.5V ESD voltage protection> 4kV data can be stored for 40 years write-protect function, when WP is high when entering the write-protected status CMOS low-power technology, Maximum write current of 3mA 128byte page write buffer auto-timing write cycle with 8-pin DIP and 20-pin SOIC package and other packages.
Platform: | Size: 43008 | Author: zhangdi | Hits:

[SCM] TFTDriverNew_V2

Description: TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
Platform: | Size: 3072 | Author: zhangming | Hits:

[VHDL-FPGA-Verilog] fifo

Description: A First in first out buffer in Verilog
Platform: | Size: 1024 | Author: Ran | Hits:

[Software Engineering] NewFolder2

Description: Verilog and VHDL programs for sipo buffer,d flip flop etc
Platform: | Size: 3072 | Author: Mallikarjun | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] transpose_buffer

Description: verilog source code for transpose buffer 8x8 matrics
Platform: | Size: 1024 | Author: abanuaji | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Platform: | Size: 432128 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] DE2_115_CAMERA

Description: d5m的DE2驱动Verilog HDL -d5m driven on DE2 by Verilog HDL
Platform: | Size: 286720 | Author: 阿凡提 | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-verilog

Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use
Platform: | Size: 14336 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] buffer

Description: 用verilog实现的buffer，经过了fpga平台验证。-Implement buffer with verilog.
Platform: | Size: 1024 | Author: yangyang | Hits:

[VHDL-FPGA-Verilog] buffer

Description: 基于verilog hdl语言的fpga缓存器buffer的一种编写 输出4组16位数-verilog hdl text for fpga of a buffer
Platform: | Size: 12288 | Author: eragon | Hits:

[VHDL-FPGA-Verilog] FLOATING-BUFFER

Description: Floating Buffer verilog code for NOC design used for dynamic reconfiguration.
Platform: | Size: 1024 | Author: guruprasad sp | Hits:

[VHDL-FPGA-Verilog] buffer

Description: Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA UNIVERSITY, CHENNAI PH:+91-9885610083
Platform: | Size: 46080 | Author: ramanna | Hits:
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