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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 231kb
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- Author ：张***
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Introduction - If you have any usage issues, please Google them yourself
VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
Packet file list
(Preview for download)
decode
......\decode.txt
......\循环码编译码方法研究.pdf
......\decode.txt
......\循环码编译码方法研究.pdf
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