Description: Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
- [FLASHROM] - JTAG port through the use of Verilog for
- [fifo] - Synchronizing FIFO creates a 256x8 synch
- [JTAG] - JTAG Verilog source code
File list (Check if you may need any files):
jtag_uart.v
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