rs on fpga decoder in the realization of the development platform used in modelsim

final_decode
............\addr_generate.vhd
............\bansui1.vhd
............\decode1.vhd
............\fangcheng
............\.........\fangcheng.vhd
............\.........\mul_decode.vhd
............\.........\testbench_fangcheng.vhd
............\fangcheng1.vhd
............\fifo.vhd
............\maichong.vhd
............\mul.vhd
............\ni_rom.vhd
............\qiansousuo1.vhd
............\ram1.vhd
............\testtop.vhd
............\top.vhd

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