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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 277kb
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  • Author :m****
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This is a hexadecimal addition and subtraction counter source code, its change it can use other hex of the
Packet file list
(Preview for download)
COUNT\db\JJ.asm.qmsg
.....\..\JJ.asm_labs.ddb
.....\..\JJ.cbx.xml
.....\..\JJ.cmp.bpm
.....\..\JJ.cmp.cdb
.....\..\JJ.cmp.ecobp
.....\..\JJ.cmp.hdb
.....\..\JJ.cmp.logdb
.....\..\JJ.cmp.rdb
.....\..\JJ.cmp.tdb
.....\..\JJ.cmp0.ddb
.....\..\JJ.cmp_bb.cdb
.....\..\JJ.cmp_bb.hdb
.....\..\JJ.cmp_bb.logdb
.....\..\JJ.cmp_bb.rcf
.....\..\JJ.dbp
.....\..\JJ.db_info
.....\..\JJ.eco.cdb
.....\..\JJ.eds_overflow
.....\..\JJ.fit.qmsg
.....\..\JJ.hier_info
.....\..\JJ.hif
.....\..\JJ.map.bpm
.....\..\JJ.map.cdb
.....\..\JJ.map.ecobp
.....\..\JJ.map.hdb
.....\..\JJ.map.logdb
.....\..\JJ.map.qmsg
.....\..\JJ.map_bb.cdb
.....\..\JJ.map_bb.hdb
.....\..\JJ.map_bb.logdb
.....\..\JJ.pre_map.cdb
.....\..\JJ.pre_map.hdb
.....\..\JJ.psp
.....\..\JJ.pss
.....\..\JJ.rtlv.hdb
.....\..\JJ.rtlv_sg.cdb
.....\..\JJ.rtlv_sg_swap.cdb
.....\..\JJ.sgdiff.cdb
.....\..\JJ.sgdiff.hdb
.....\..\JJ.signalprobe.cdb
.....\..\JJ.sim.cvwf
.....\..\JJ.sim.hdb
.....\..\JJ.sim.qmsg
.....\..\JJ.sim.rdb
.....\..\JJ.sld_design_entry.sci
.....\..\JJ.sld_design_entry_dsc.sci
.....\..\JJ.syn_hier_info
.....\..\JJ.tan.qmsg
.....\..\JJ.tis_db_list.ddb
.....\..\prev_cmp_JJ.asm.qmsg
.....\..\prev_cmp_JJ.fit.qmsg
.....\..\prev_cmp_JJ.map.qmsg
.....\..\prev_cmp_JJ.qmsg
.....\..\prev_cmp_JJ.sim.qmsg
.....\..\prev_cmp_JJ.tan.qmsg
.....\..\wed.wsf
.....\JJ.asm.rpt
.....\JJ.bsf
.....\JJ.done
.....\JJ.fit.rpt
.....\JJ.fit.smsg
.....\JJ.fit.summary
.....\JJ.flow.rpt
.....\JJ.inc
.....\JJ.map.rpt
.....\JJ.map.summary
.....\JJ.pin
.....\JJ.pof
.....\JJ.qpf
.....\JJ.qsf
.....\JJ.sim.rpt
.....\JJ.sof
.....\JJ.tan.rpt
.....\JJ.tan.summary
.....\JJ.vhd
.....\JJ.vhd.bak
.....\JJ.vwf
.....\Waveform1.vwf
.....\db
COUNT
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